test.tfw

实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 9.1i
//  \   \         Application : ISE
//  /   /         Filename : Test.tfw
// /___/   /\     Timestamp : Fri Mar 27 15:35:24 2009
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: Test
//Device: Xilinx
//
`timescale 1ns/1ps

module Test;
    reg ARE = 1'b0;
    reg AOE = 1'b0;
    reg AWE = 1'b0;
    reg CE2 = 1'b0;
    wire [3:0] EXT_INT;
    reg CLKOUT2 = 1'b0;
    reg [3:0] TEA = 4'b0000;
    reg [15:0] TED$inout$reg = 16'b0000000000000000;
    wire [15:0] TED = TED$inout$reg;
    wire [7:0] LED_OUT;
    reg RST = 1'b0;

    parameter PERIOD = 10;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 20;

    initial    // Clock process for CLKOUT2
    begin
        #OFFSET;
        forever
        begin
            CLKOUT2 = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) CLKOUT2 = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

    EMIF_COM UUT (
        .ARE(ARE),
        .AOE(AOE),
        .AWE(AWE),
        .CE2(CE2),
        .EXT_INT(EXT_INT),
        .CLKOUT2(CLKOUT2),
        .TEA(TEA),
        .TED(TED),
        .LED_OUT(LED_OUT),
        .RST(RST));

    initial begin
        // -------------  Current Time:  10ns
        #10;
        CE2 = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  14ns
        #4;
        AOE = 1'b1;
        ARE = 1'b1;
        AWE = 1'b1;
        RST = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  123ns
        #108;
        RST = 1'b0;
        // -------------------------------------
        // -------------  Current Time:  193ns
        #70;
        RST = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  253ns
        #60;
        CE2 = 1'b0;
        TED$inout$reg = 16'b1001100110011001;
        // -------------------------------------
        // -------------  Current Time:  263ns
        #10;
        AWE = 1'b0;
        TEA = 4'b1001;
        // -------------------------------------
        // -------------  Current Time:  273ns
        #10;
        AWE = 1'b1;
        TEA = 4'b0000;
        // -------------------------------------
        // -------------  Current Time:  283ns
        #10;
        CE2 = 1'b1;
        TED$inout$reg = 16'bZZZZZZZZZZZZZZZZ;
        // -------------------------------------
        // -------------  Current Time:  653ns
        #370;
        AOE = 1'b0;
        CE2 = 1'b0;
        TEA = 4'b1001;
        // -------------------------------------
        // -------------  Current Time:  663ns
        #10;
        ARE = 1'b0;
        // -------------------------------------
        // -------------  Current Time:  673ns
        #10;
        ARE = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  683ns
        #10;
        AOE = 1'b1;
        CE2 = 1'b1;
        TEA = 4'b0000;
        // -------------------------------------
    end

endmodule