par.xmsgs

来自「实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口」· XMSGS 代码 · 共 24 行

<?xml version="1.0" encoding="UTF-8"?>
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     by the Xilinx ISE software.  Any direct editing or
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<messages>
<msg type="info" file="Par" num="282" delta="unknown" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;.  For best performance, set the effort level to &quot;high&quot;. For a balance between the fastest runtime and best performance, set the effort level to &quot;med&quot;.
</msg>

<msg type="warning" file="Par" num="288" delta="unknown" >The signal <arg fmt="%s" index="1">CLKOUT2_IBUF</arg> has no load.  PAR will not attempt to route this signal.
</msg>

<msg type="warning" file="Par" num="283" delta="unknown" >There are <arg fmt="%d" index="1">1</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

</msg>

<msg type="warning" file="ParHelpers" num="361" delta="unknown" >There are <arg fmt="%d" index="1">1</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

</msg>

</messages>