📄 s3c2410.h
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S3C24X0_REG8 res5[3];
S3C24X0_REG8 EP_DMA_TTC_M;
S3C24X0_REG8 res6[3];
S3C24X0_REG8 EP_DMA_TTC_H;
#else /* little endian */
S3C24X0_REG8 EP_DMA_CON;
S3C24X0_REG8 res1[3];
S3C24X0_REG8 EP_DMA_UNIT;
S3C24X0_REG8 res2[3];
S3C24X0_REG8 EP_DMA_FIFO;
S3C24X0_REG8 res3[3];
S3C24X0_REG8 EP_DMA_TTC_L;
S3C24X0_REG8 res4[3];
S3C24X0_REG8 EP_DMA_TTC_M;
S3C24X0_REG8 res5[3];
S3C24X0_REG8 EP_DMA_TTC_H;
S3C24X0_REG8 res6[3];
#endif
}
/*__attribute__((__packed__))*/ S3C24X0_USB_DEV_DMAS;
typedef struct
{
#ifdef __BIG_ENDIAN
S3C24X0_REG8 res1[3];
S3C24X0_REG8 FUNC_ADDR_REG;
S3C24X0_REG8 res2[3];
S3C24X0_REG8 PWR_REG;
S3C24X0_REG8 res3[3];
S3C24X0_REG8 EP_INT_REG;
S3C24X0_REG8 res4[15];
S3C24X0_REG8 USB_INT_REG;
S3C24X0_REG8 res5[3];
S3C24X0_REG8 EP_INT_EN_REG;
S3C24X0_REG8 res6[15];
S3C24X0_REG8 USB_INT_EN_REG;
S3C24X0_REG8 res7[3];
S3C24X0_REG8 FRAME_NUM1_REG;
S3C24X0_REG8 res8[3];
S3C24X0_REG8 FRAME_NUM2_REG;
S3C24X0_REG8 res9[3];
S3C24X0_REG8 INDEX_REG;
S3C24X0_REG8 res10[7];
S3C24X0_REG8 MAXP_REG;
S3C24X0_REG8 res11[3];
S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
S3C24X0_REG8 res12[3];
S3C24X0_REG8 IN_CSR2_REG;
S3C24X0_REG8 res13[7];
S3C24X0_REG8 OUT_CSR1_REG;
S3C24X0_REG8 res14[3];
S3C24X0_REG8 OUT_CSR2_REG;
S3C24X0_REG8 res15[3];
S3C24X0_REG8 OUT_FIFO_CNT1_REG;
S3C24X0_REG8 res16[3];
S3C24X0_REG8 OUT_FIFO_CNT2_REG;
#else /* little endian */
S3C24X0_REG8 FUNC_ADDR_REG;
S3C24X0_REG8 res1[3];
S3C24X0_REG8 PWR_REG;
S3C24X0_REG8 res2[3];
S3C24X0_REG8 EP_INT_REG;
S3C24X0_REG8 res3[15];
S3C24X0_REG8 USB_INT_REG;
S3C24X0_REG8 res4[3];
S3C24X0_REG8 EP_INT_EN_REG;
S3C24X0_REG8 res5[15];
S3C24X0_REG8 USB_INT_EN_REG;
S3C24X0_REG8 res6[3];
S3C24X0_REG8 FRAME_NUM1_REG;
S3C24X0_REG8 res7[3];
S3C24X0_REG8 FRAME_NUM2_REG;
S3C24X0_REG8 res8[3];
S3C24X0_REG8 INDEX_REG;
S3C24X0_REG8 res9[7];
S3C24X0_REG8 MAXP_REG;
S3C24X0_REG8 res10[7];
S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
S3C24X0_REG8 res11[3];
S3C24X0_REG8 IN_CSR2_REG;
S3C24X0_REG8 res12[3];
S3C24X0_REG8 OUT_CSR1_REG;
S3C24X0_REG8 res13[7];
S3C24X0_REG8 OUT_CSR2_REG;
S3C24X0_REG8 res14[3];
S3C24X0_REG8 OUT_FIFO_CNT1_REG;
S3C24X0_REG8 res15[3];
S3C24X0_REG8 OUT_FIFO_CNT2_REG;
S3C24X0_REG8 res16[3];
#endif /* __BIG_ENDIAN */
S3C24X0_USB_DEV_FIFOS fifo[5];
S3C24X0_USB_DEV_DMAS dma[5];
}
/*__attribute__((__packed__))*/ S3C24X0_USB_DEVICE;
/* WATCH DOG TIMER (see manual chapter 18) */
typedef struct
{
S3C24X0_REG32 WTCON;
S3C24X0_REG32 WTDAT;
S3C24X0_REG32 WTCNT;
}
/*__attribute__((__packed__))*/ S3C24X0_WATCHDOG;
/* IIC (see manual chapter 20) */
typedef struct
{
S3C24X0_REG32 IICCON;
S3C24X0_REG32 IICSTAT;
S3C24X0_REG32 IICADD;
S3C24X0_REG32 IICDS;
}
/*__attribute__((__packed__))*/ S3C24X0_I2C;
/* IIS (see manual chapter 21) */
typedef struct
{
#ifdef __BIG_ENDIAN
S3C24X0_REG16 res1;
S3C24X0_REG16 IISCON;
S3C24X0_REG16 res2;
S3C24X0_REG16 IISMOD;
S3C24X0_REG16 res3;
S3C24X0_REG16 IISPSR;
S3C24X0_REG16 res4;
S3C24X0_REG16 IISFCON;
S3C24X0_REG16 res5;
S3C24X0_REG16 IISFIFO;
#else /* little endian */
S3C24X0_REG16 IISCON;
S3C24X0_REG16 res1;
S3C24X0_REG16 IISMOD;
S3C24X0_REG16 res2;
S3C24X0_REG16 IISPSR;
S3C24X0_REG16 res3;
S3C24X0_REG16 IISFCON;
S3C24X0_REG16 res4;
S3C24X0_REG16 IISFIFO;
S3C24X0_REG16 res5;
#endif
}
/*__attribute__((__packed__))*/ S3C24X0_I2S;
/* I/O PORT (see manual chapter 9) */
typedef struct
{
S3C24X0_REG32 GPACON;
S3C24X0_REG32 GPADAT;
S3C24X0_REG32 res1[2];
S3C24X0_REG32 GPBCON;
S3C24X0_REG32 GPBDAT;
S3C24X0_REG32 GPBUP;
S3C24X0_REG32 res2;
S3C24X0_REG32 GPCCON;
S3C24X0_REG32 GPCDAT;
S3C24X0_REG32 GPCUP;
S3C24X0_REG32 res3;
S3C24X0_REG32 GPDCON;
S3C24X0_REG32 GPDDAT;
S3C24X0_REG32 GPDUP;
S3C24X0_REG32 res4;
S3C24X0_REG32 GPECON;
S3C24X0_REG32 GPEDAT;
S3C24X0_REG32 GPEUP;
S3C24X0_REG32 res5;
S3C24X0_REG32 GPFCON;
S3C24X0_REG32 GPFDAT;
S3C24X0_REG32 GPFUP;
S3C24X0_REG32 res6;
S3C24X0_REG32 GPGCON;
S3C24X0_REG32 GPGDAT;
S3C24X0_REG32 GPGUP;
S3C24X0_REG32 res7;
S3C24X0_REG32 GPHCON;
S3C24X0_REG32 GPHDAT;
S3C24X0_REG32 GPHUP;
S3C24X0_REG32 res8;
S3C24X0_REG32 MISCCR;
S3C24X0_REG32 DCLKCON;
S3C24X0_REG32 EXTINT0;
S3C24X0_REG32 EXTINT1;
S3C24X0_REG32 EXTINT2;
S3C24X0_REG32 EINTFLT0;
S3C24X0_REG32 EINTFLT1;
S3C24X0_REG32 EINTFLT2;
S3C24X0_REG32 EINTFLT3;
S3C24X0_REG32 EINTMASK;
S3C24X0_REG32 EINTPEND;
S3C24X0_REG32 GSTATUS0;
S3C24X0_REG32 GSTATUS1;
S3C24X0_REG32 GSTATUS2;
S3C24X0_REG32 GSTATUS3;
S3C24X0_REG32 GSTATUS4;
}
/*__attribute__((__packed__))*/ S3C24X0_GPIO;
/* S3C2410 device base addresses */
#define S3C24X0_MEMCTL_BASE 0x48000000
#define S3C24X0_USB_HOST_BASE 0x49000000
#define S3C24X0_INTERRUPT_BASE 0x4A000000
#define S3C24X0_DMA_BASE 0x4B000000
#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
#define S3C24X0_LCD_BASE 0x4D000000
#define S3C2410_NAND_BASE 0x4E000000
#define S3C24X0_UART_BASE 0x50000000
#define S3C24X0_TIMER_BASE 0x51000000
#define S3C24X0_USB_DEVICE_BASE 0x52000140
#define S3C24X0_WATCHDOG_BASE 0x53000000
#define S3C24X0_I2C_BASE 0x54000000
#define S3C24X0_I2S_BASE 0x55000000
#define S3C24X0_GPIO_BASE 0x56000000
#define S3C24X0_RTC_BASE 0x57000000
#define S3C2410_ADC_BASE 0x58000000
#define S3C24X0_SPI_BASE 0x59000000
#define S3C2410_SDI_BASE 0x5A000000
// Memory control
#define rBWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status
#define rBANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control
#define rBANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control
#define rBANKCON2 (*(volatile unsigned *)0x4800000c) //BANK2 cControl
#define rBANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control
#define rBANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control
#define rBANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control
#define rBANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control
#define rBANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control
#define rREFRESH (*(volatile unsigned *)0x48000024) //DRAM/SDRAM refresh
#define rBANKSIZE (*(volatile unsigned *)0x48000028) //Flexible Bank Size
#define rMRSRB6 (*(volatile unsigned *)0x4800002c) //Mode register set for SDRAM
#define rMRSRB7 (*(volatile unsigned *)0x48000030) //Mode register set for SDRAM
/* USB HOST */
#define rHcRevision (*(volatile unsigned *)0x49000000)
#define rHcControl (*(volatile unsigned *)0x49000004)
#define rHcCommonStatus (*(volatile unsigned *)0x49000008)
#define rHcInterruptStatus (*(volatile unsigned *)0x4900000C)
#define rHcInterruptEnable (*(volatile unsigned *)0x49000010)
#define rHcInterruptDisable (*(volatile unsigned *)0x49000014)
#define rHcHCCA (*(volatile unsigned *)0x49000018)
#define rHcPeriodCuttendED (*(volatile unsigned *)0x4900001C)
#define rHcControlHeadED (*(volatile unsigned *)0x49000020)
#define rHcControlCurrentED (*(volatile unsigned *)0x49000024)
#define rHcBulkHeadED (*(volatile unsigned *)0x49000028)
#define rHcBuldCurrentED (*(volatile unsigned *)0x4900002C)
#define rHcDoneHead (*(volatile unsigned *)0x49000030)
#define rHcRmInterval (*(volatile unsigned *)0x49000034)
#define rHcFmRemaining (*(volatile unsigned *)0x49000038)
#define rHcFmNumber (*(volatile unsigned *)0x4900003C)
#define rHcPeriodicStart (*(volatile unsigned *)0x49000040)
#define rHcLSThreshold (*(volatile unsigned *)0x49000044)
#define rHcRhDescriptorA (*(volatile unsigned *)0x49000048)
#define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C)
#define rHcRhStatus (*(volatile unsigned *)0x49000050)
#define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054)
#define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058)
// INTERRUPT
#define rSRCPND (*(volatile unsigned *)0x4a000000) //Interrupt request status
#define rINTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control
#define rINTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control
#define rPRIORITY (*(volatile unsigned *)0x4a00000c) //IRQ priority control
#define rINTPND (*(volatile unsigned *)0x4a000010) //Interrupt request status
#define rINTOFFSET (*(volatile unsigned *)0x4a000014) //Interruot request source offset
#define rSUBSRCPND (*(volatile unsigned *)0x4a000018) //Sub source pending
#define rINTSUBMSK (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask
// DMA
#define rDISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source
#define rDISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control
#define rDIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination
#define rDIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control
#define rDCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control
#define rDSTAT0 (*(volatile unsigned *)0x4b000014) //DMA 0 Status
#define rDCSRC0 (*(volatile unsigned *)0x4b000018) //DMA 0 Current source
#define rDCDST0 (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination
#define rDMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger
#define rDISRC1 (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source
#define rDISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control
#define rDIDST1 (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination
#define rDIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control
#define rDCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control
#define rDSTAT1 (*(volatile unsigned *)0x4b000054) //DMA 1 Status
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