lpc32xx_emc.h

NXP LPC3000系列 wince BSP包

/* Macro for setting the precharge command period */
#define EMC_DYN_PRE_CMD_PER(n)     ((n) & 0xF)

/***********************************************************************
* emcdynamictras register defines
**********************************************************************/
/* Macro for setting the active to precharge command period */
#define EMC_DYN_ACTPRE_CMD_PER(n)  ((n) & 0xF)

/***********************************************************************
* emcdynamictsrex register defines
**********************************************************************/
/* Macro for setting the self refresh exit time */
#define EMC_DYN_SELF_RFSH_EXIT(n)  ((n) & 0x7F)

/***********************************************************************
* emcdynamictwr register defines
**********************************************************************/
/* Macro for setting the write recover time */
#define EMC_DYN_WR_RECOVERT_TIME(n) ((n) & 0xF)

/***********************************************************************
* emcdynamictrc register defines
**********************************************************************/
/* Macro for setting the active to command period */
#define EMC_DYN_ACT2CMD_PER(n)     ((n) & 0x1F)

/***********************************************************************
* emcdynamictrfc register defines
**********************************************************************/
/* Macro for setting the auto-refresh period */
#define EMC_DYN_AUTOREFRESH_PER(n) ((n) & 0x1F)

/***********************************************************************
* emcdynamictxsr register defines
**********************************************************************/
/* Macro for setting the exit self-refresh time */
#define EMC_DYN_EXIT_SRFSH_TIME(n) ((n) & 0xFF)

/***********************************************************************
* emcdynamictrrd register defines
**********************************************************************/
/* Macro for setting the active bank A to bank B latency time */
#define EMC_DYN_BANKA2BANKB_LAT(n) ((n) & 0xF)

/***********************************************************************
* emcdynamictmrd register defines
**********************************************************************/
/* Macro for setting the load mode register to active command time */
#define EMC_DYN_LM2ACT_CMD_TIME(n) ((n) & 0xF)

/***********************************************************************
* emcdynamictcdlr register defines
**********************************************************************/
/* Macro for setting the last daat-in to read command time */
#define EMC_DYN_LASTDIN_CMD_TIME(n) ((n) & 0xF)

/***********************************************************************
* emcstaticextendedwait register defines
**********************************************************************/
/* Macro for setting the extended wait time time */
#define EMC_STC_EXT_WAIT_TIME(n)   ((n) & 0x1FF)

/***********************************************************************
* emcdynamicconfig0, emcdynamicconfig1 register defines
***********************************************************************/
/* Write protect enable */
#define EMC_DYN_WR_PROTECT_EN      __BIT(20)
/* Address mapping modes mask, see documentation for mode selection */
#define EMC_DYN_ADDR_MAP_MASK      0x00007F80
/* Memory device selections */
#define EMC_DYN_DEV_SDR_SDRAM      0x00000000 /* SDR SDRAM */
#define EMC_DYN_DEV_LP_SDR_SDRAM   0x00000002 /* Low power SDR SDRAM */
#define EMC_DYN_DEV_DDR_SDRAM      0x00000004 /* DDR SDRAM */
#define EMC_DYN_DEV_LP_DDR_SDRAM   0x00000006 /* Low power DDR SDRAM */

/***********************************************************************
* emcdynamicrascas0, emcdynamicrascas1 register defines
***********************************************************************/
/* Macro for loading CAS latency in 1/2 clock cycles */
#define EMC_SET_CAS_IN_HALF_CYCLES(n) (((n) & 0xF) << 7)
/* Macro for loading RAS latency in clock cycles, n = 1 to 15 */
#define EMC_SET_RAS_IN_CYCLES(n) ((n) & 0xF)

/***********************************************************************
* emcstaticconfig register defines
***********************************************************************/
/* Static memory interface write protect bit */
#define EMC_STC_WP_BIT             _BIT(20)
/* Static memory interface extended wait enable bit */
#define EMC_STC_EXT_WAIT_EN_BIT    _BIT(8)
/* Static memory Byte lane signals enable bit */
#define EMC_STC_BLS_EN_BIT         _BIT(7)
/* Static memory select high chip select polarity enable bit */
#define EMC_STC_CS_POL_HIGH_BIT    _BIT(6)
/* Static memory page mode enable bit */
#define EMC_STC_PAGEMODE_EN_BIT    _BIT(3)
/* Static memory memory width selections */
#define EMC_STC_MEMWIDTH_8         0x00000000
#define EMC_STC_MEMWIDTH_16        0x00000001
#define EMC_STC_MEMWIDTH_32        0x00000002

/* Static memory memory chip selects */
#define EMC_STC_CS0        0x00000000
#define EMC_STC_CS1        0x00000001
#define EMC_STC_CS2        0x00000002
#define EMC_STC_CS3        0x00000003

/***********************************************************************
* emcstaticwaitwen register defines
***********************************************************************/
/* Macro for loading the chip select to wait write enable delay,
   (cs->we) n = 0 to 15 */
#define EMC_STC_WAIT_WR_DELAY(n)   ((n) & 0xF)

/***********************************************************************
* emcstaticwait0en register defines
***********************************************************************/
/* Macro for loading the chip select to output enable delay, (cs->oe)
   n = 0 to 15 */
#define EMC_STC_CS2OE_DELAY(n)     ((n) & 0xF)

/***********************************************************************
* emcstaticwaitrd register defines
***********************************************************************/
/* Macro for loading the first read delay in page mode, n = 0 to 15 */
#define EMC_STC_RDPAGEMODE_DELAY1(n) ((n) & 0x1F)

/***********************************************************************
* emcstaticpage register defines
***********************************************************************/
/* Macro for loading the 2nd, 3rd, and 4rth read delay in page
   mode, n = 0 to 15 */
#define EMC_STC_RDPAGEMODE_DELAY234(n) ((n) & 0x1F)

/***********************************************************************
* emcstaticwr register defines
***********************************************************************/
/* Macro for loading the 2nd, 3rd, and 4rth write delay in page
   mode, n = 0 to 15 */
#define EMC_STC_WRPAGEMODE_DELAY234(n) ((n) & 0x1F)

/***********************************************************************
* emcstaticturn register defines
***********************************************************************/
/* Macro for loading the bus turnaround time, n = 0 to 15 */
#define EMC_STC_BUSTURNAROUND_DELAY(n) ((n) & 0xF)

/***********************************************************************
* emcahbcontrol register defines
***********************************************************************/
/* Bit for enabling the AHB port buffer */
#define EMC_AHB_PORTBUFF_EN        0x1

/***********************************************************************
* emcahbstatus register defines
***********************************************************************/
/* AHB buffer not empty status bit mask */
#define EMC_AHB_PORTBUFF_NOT_MT    0x2

/***********************************************************************
* emcahbtimeout register defines
***********************************************************************/
/* Macro for loading the AHB timeout in clocks, n = 0 to 1023 */
#define EMC_AHB_SET_TIMEOUT(n)     ((n) & 0x1FF)

/* Macro pointing to EMC registers */
#define EMC  ((EMC_REGS_T *)(EMC_BASE))

#endif /* LPC32XX_EMC_H */