lpc32xx_emc.h

NXP LPC3000系列 wince BSP包

/***********************************************************************
* $Id:: lpc32xx_emc.h 1101 2008-08-20 22:25:30Z wellsk                $
*
* Project: LPC32XX chip family External Memory Controller definitions
*
* Description:
*     This file contains the structure definitions and manifest
*     constants for the LPC32XX chip family component:
*         External Memory Controller
*
***********************************************************************
* Software that is described herein is for illustrative purposes only  
* which provides customers with programming information regarding the  
* products. This software is supplied "AS IS" without any warranties.  
* NXP Semiconductors assumes no responsibility or liability for the 
* use of the software, conveys no license or title under any patent, 
* copyright, or mask work right to the product. NXP Semiconductors 
* reserves the right to make changes in the software without 
* notification. NXP Semiconductors also make no representation or 
* warranty that such application will be suitable for the specified 
* use without further testing or modification. 
**********************************************************************/

#ifndef LPC32XX_EMC_H
#define LPC32XX_EMC_H

#include "lpc_types.h"
#include "lpc32xx_chip.h"

/***********************************************************************
* External Memory Controller Module Register Structure
**********************************************************************/

/* Static chip select configuration structure */
typedef struct
{
	volatile UNS_32 emcstaticconfig;       /* Memory config reg */
	volatile UNS_32 emcstaticwaitwen;      /* cs->we delay reg */
	volatile UNS_32 emcstaticwait0en;      /* cs->oe delay reg */
	volatile UNS_32 emcstaticwaitrd;       /* cs->rd delay reg */
	volatile UNS_32 emcstaticpage;         /* async page delay reg */
	volatile UNS_32 emcstaticwr;           /* cs->wr delay reg */
	volatile UNS_32 emcstaticturn;         /* bus turnaround delay reg */
	volatile UNS_32 reserved;
} EMC_STATIC_CFG;

/*  AHB control structure */
typedef struct
{
	volatile UNS_32 emcahbcontrol;
	volatile UNS_32 emcahbstatus;
	volatile UNS_32 emcahbtimeout;
	volatile UNS_32 reserved [5];
} EMC_AHB_CTRL_T;

/* External Memory Controller Module Register Structure */
typedef struct 
{
	volatile UNS_32 emccontrol;           /* EMC control reg */
	volatile UNS_32 emcstatus;            /* SDRAM status reg */
	volatile UNS_32 emcconfig;            /* EMC config reg */
    volatile UNS_32 reserved1 [5];
	volatile UNS_32 emcdynamiccontrol;    /* Dynamic mem control reg */
	volatile UNS_32 emcdynamicrefresh;    /* Dynamic mem refresh reg */
	volatile UNS_32 emcdynamicreadconfig; /* Dynamic mem read ctrl */
    volatile UNS_32 reserved2;
	volatile UNS_32 emcdynamictrp;        /* Pre cmd period reg */
	volatile UNS_32 emcdynamictras;       /* Act->pre cmd period reg */
	volatile UNS_32 emcdynamictsrex;      /* Self refresh exit time */
    volatile UNS_32 reserved3 [2];
	volatile UNS_32 emcdynamictwr;        /* Write recovery time */
	volatile UNS_32 emcdynamictrc;        /* Act->act cmd period reg */
	volatile UNS_32 emcdynamictrfc;       /* Auto-refresh period reg */
	volatile UNS_32 emcdynamictxsr;       /* Self->act cmd period reg */
	volatile UNS_32 emcdynamictrrd;       /* Bank switch latency reg */
	volatile UNS_32 emcdynamictmrd;       /* Load mode to active reg */
	volatile UNS_32 emcdynamictcdlr;      /* read->act cmd period reg */
    volatile UNS_32 reserved4 [8];
	volatile UNS_32 emcstaticextendedwait;/* Long read/write delay reg */
    volatile UNS_32 reserved5 [31];
	volatile UNS_32 emcdynamicconfig0;    /* Config info 0 reg */
	volatile UNS_32 emcdynamicrascas0;    /* RAS/CAS latencies 0 reg */
	volatile UNS_32 reserved6 [6];
    volatile UNS_32 emcdynamicconfig1;    /* Config info 1 reg */
    volatile UNS_32 emcdynamicrascas1;    /* RAS/CAS latencies 1 reg */
    volatile UNS_32 reserved7 [54];
	EMC_STATIC_CFG  emcstatic_regs [4];   /* Static controller regs */
    volatile UNS_32 reserved8 [96];
	EMC_AHB_CTRL_T  emcahn_regs [5];      /* EMC AHB control regs */
} EMC_REGS_T;

/***********************************************************************
* emccontrol register defines
**********************************************************************/
/* Dynamic controller low power mode bit */
#define EMC_DYN_LP_MODE            _BIT(2)
/* SDRAM controller enable bit */
#define EMC_DYN_SDRAM_CTRL_EN      _BIT(0)

/***********************************************************************
* emcstatus register defines
**********************************************************************/
/* Self-refesh mode status bit */
#define EMC_DYN_SELFRESH_MODE_BIT  _BIT(2)
/* SDRAM controller busy status bit */
#define EMC_DYN_CTRL_BUSY_BIT      _BIT(0)

/***********************************************************************
* emcconfig register defines
**********************************************************************/
/* SDRAM Big-endian mode bit */
#define EMC_DYN_ENDIAN_MODE_BIT    _BIT(0)

/***********************************************************************
* emcdynamiccontrol register defines
**********************************************************************/
/* Enter deep sleep power down mode bit */
#define EMC_DYN_DEEPDLEEP_BIT      _BIT(13)
/* SDRAM normal mode state */
#define EMC_DYN_NORMAL_MODE        0x00000000
#define EMC_DYN_CMD_MODE           0x00000080
#define EMC_DYN_PALL_MODE          0x00000100
#define EMC_DYN_NOP_MODE           0x00000180
/* Mask to get the current SDRAM mode */
#define EMC_DYN_MODE_MASK          0x00000180
/* Disable (1) or enable (0) memory clock bit */
#define EMC_DYN_DIS_MEMCLK         _BIT(5)
/* Disable (1) or enable (0) inverted memory clock bit */
#define EMC_DYN_DIS_INV_MEMCLK     _BIT(4)
/* Disable (1) or enable (0) memory clock during self-refresh bit */
#define EMC_DYN_DIS_MEMCLK_IN_SFRSH _BIT(3)
/* Enter self refresh request bit */
#define EMC_DYN_REQ_SELF_REFRESH   _BIT(2)
/* RAM clock runs continuously (1) or os stops when idle (0) bit */
#define EMC_DYN_CLK_ALWAYS_ON      _BIT(1)
/* RAM clock enables are always driven high bit */
#define EMC_DYN_CLKEN_ALWAYS_ON    _BIT(0)

/***********************************************************************
* emcdynamicrefresh register defines
**********************************************************************/
/* Macro for loading the SDRAM refresh interval in groups of 16
   clocks */
#define EMC_DYN_REFRESH_IVAL(n)    (((n) >> 4) & 0x7FF)

/***********************************************************************
* emcdynamicreadconfig register defines
**********************************************************************/
/* DDR capture polarity is postive edge of HCLK */
#define EMC_DDR_READCAP_POS_POL    _BIT(12)
/* DDR capture strategy: Clock out delay, command not delayed */
#define EMC_DDR_CLK_DLY_CMD_NODELY 0x00000000
/* DDR capture strategy: Clock out not delay, command delayed */
#define EMC_DDR_CLK_NODLY_CMD_DEL  0x00000100
/* DDR capture strategy: Clock out not delay, command delayed plus 1 clk */
#define EMC_DDR_CLK_NODLY_CMD_DEL1 0x00000200
/* DDR capture strategy: Clock out not delay, command delayed plus 2 clk */
#define EMC_DDR_CLK_NODLY_CMD_DEL2 0x00000300
/* SDRAM read polarity is postive edge of HCLK */
#define EMC_SDR_READCAP_POS_POL    _BIT(4)
/* SDRAM read strategy: Clock out delay, command not delayed */
#define EMC_SDR_CLK_DLY_CMD_NODELY 0x00000000
/* SDRAM read strategy: Clock out not delay, command delayed */
#define EMC_SDR_CLK_NODLY_CMD_DEL  0x00000001
/* SDRAM read strategy: Clock out not delay, command delayed plus 1 clk */
#define EMC_SDR_CLK_NODLY_CMD_DEL1 0x00000002
/* SDRAM read strategy: Clock out not delay, command delayed plus 2 clk */
#define EMC_SDr_CLK_NODLY_CMD_DEL2 0x00000003

/***********************************************************************
* emcdynamictrp register defines
**********************************************************************/