lpc32xx_mac.h

NXP LPC3000系列 wince BSP包

/***********************************************************************
* $Id:: lpc32xx_mac.h 1101 2008-08-20 22:25:30Z wellsk                $
*
* Project: LPC32XX ethernet MAC controller definitions
*
* Description:
*     This file contains the structure definitions and manifest
*     constants for the LPC32xx chip family component:
*         ethernet MAC
*
***********************************************************************
* Software that is described herein is for illustrative purposes only  
* which provides customers with programming information regarding the  
* products. This software is supplied "AS IS" without any warranties.  
* NXP Semiconductors assumes no responsibility or liability for the 
* use of the software, conveys no license or title under any patent, 
* copyright, or mask work right to the product. NXP Semiconductors 
* reserves the right to make changes in the software without 
* notification. NXP Semiconductors also make no representation or 
* warranty that such application will be suitable for the specified 
* use without further testing or modification. 
**********************************************************************/

#ifndef LPC32XX_MAC_H
#define LPC32XX_MAC_H

#include "lpc_types.h"
#include "lpc32xx_chip.h"

#ifdef __cplusplus
extern "C" {
#endif

/**********************************************************************
* Ethernet MAC controller register structures
**********************************************************************/

/* Ethernet MAC controller module register structures */ 
typedef struct {
	/* MAC registers */
	volatile UNS_32 mac1;          /* MAC config1 register */
	volatile UNS_32 mac2;          /* MAC config2 register */
	volatile UNS_32 ipgt;          /* MAC b2b interpack gap register */
	volatile UNS_32 ipgr;          /* MAC nb2b interpack gap register */
	volatile UNS_32 clrt;          /* MAC collision retry register */
	volatile UNS_32 maxf;          /* MAC Maximum frame register */
	volatile UNS_32 supp;          /* MAC PHY support register */
	volatile UNS_32 test;          /* MAC test register */
	volatile UNS_32 mcfg;          /* MAC MII mgmt config register */
	volatile UNS_32 mcmd;          /* MAC MII mgmt command register */
	volatile UNS_32 madr;          /* MAC MII mgmt address register */
	volatile UNS_32 mwtd;          /* MAC MII mgmt write register */
	volatile UNS_32 mrdd;          /* MAC MII mgmt read register */
	volatile UNS_32 mind;          /* MAC MII mgmt indicators reg */
	volatile UNS_32 reserved1 [2];
	volatile UNS_32 sa [3];        /* Station address registers */
	volatile UNS_32 reserved2 [45];
	/* Control registers */
	volatile UNS_32 command;
	volatile UNS_32 status;
	volatile UNS_32 rxdescriptor;
	volatile UNS_32 rxstatus;
	volatile UNS_32 rxdescriptornumber;
	volatile UNS_32 rxproduceindex;
	volatile UNS_32 rxconsumeindex;
	volatile UNS_32 txdescriptor;
	volatile UNS_32 txstatus;
	volatile UNS_32 txdescriptornumber;
	volatile UNS_32 txproduceindex;
	volatile UNS_32 txconsumeindex;
	volatile UNS_32 reserved3 [10];
	volatile UNS_32 tsv0;
	volatile UNS_32 tsv1;
	volatile UNS_32 rsv;
	volatile UNS_32 reserved4 [3];
	volatile UNS_32 flowcontrolcounter;
	volatile UNS_32 flowcontrolstatus;
	volatile UNS_32 reserved5 [34];
	/* RX filter registers */
	volatile UNS_32 rxfliterctrl;
	volatile UNS_32 rxfilterwolstatus;
	volatile UNS_32 rxfilterwolclear;
	volatile UNS_32 reserved6;
	volatile UNS_32 hashfilterL;
	volatile UNS_32 hashfilterh;
	volatile UNS_32 reserved7 [882];
	/* Module control registers */
	volatile UNS_32 intstatus;
	volatile UNS_32 intenable;
	volatile UNS_32 intclear;
	volatile UNS_32 Intset;
	volatile UNS_32 reserved8;
	volatile UNS_32 powerdown;
	volatile UNS_32 reserved9;
} ETHERNET_REGS_T;

/* Structure of a TX/RX descriptor */
typedef struct {
	volatile UNS_32 packet;
	volatile UNS_32 control;
} TXRX_DESC_T;

/* Structure of a RX status entry */
typedef struct {
	volatile UNS_32 statusinfo;
	volatile UNS_32 statushashcrc;
} RX_STATUS_T;

/**********************************************************************
* mac1 register definitions
**********************************************************************/
/* Set this to allow receive frames to be received. Internally the
   MAC synchronize this control bit to the incoming receive stream */
#define MAC1_RECV_ENABLE               _BIT(0)
/* When enabled (set to