lpc32xx_clkpwr.h

NXP LPC3000系列 wince BSP包

#define CLKPWR_I2SCTRL_I2S1_USE_DMA _BIT(4)
/* I2S0 TX clock mode, (0) = TX clock drives TX timing, (1) = RX clock
   drives TX timing */
#define CLKPWR_I2SCTRL_I2S0_RX_FOR_TX _BIT(3)
/* I2S0 RX clock mode, (0) = RX clock drives RX timing, (1) = TX clock
   drives RX timing */
#define CLKPWR_I2SCTRL_I2S0_TX_FOR_RX _BIT(2)
/* I2S1 clock disable (0) / enable (1) bit */
#define CLKPWR_I2SCTRL_I2SCLK1_EN  _BIT(1)
/* I2S0 clock disable (0) / enable (1) bit */
#define CLKPWR_I2SCTRL_I2SCLK0_EN  _BIT(0)

/**********************************************************************
* clkpwr_ms_ctrl register definitions
**********************************************************************/
/* MSSDIO pullup enable (1) / disable (0) */
#define CLKPWR_MSCARD_MSDIO_PU_EN  _BIT(9)
/* MSSDIO data 2 and 3 pullup disable (1) / enable (0) */
#define CLKPWR_MSCARD_MSDIO23_DIS  _BIT(8)
/* MSSDIO data 1 pullup disable (1) / enable (0) */
#define CLKPWR_MSCARD_MSDIO1_DIS   _BIT(7)
/* MSSDIO data 0 pullup disable (1) / enable (0) */
#define CLKPWR_MSCARD_MSDIO0_DIS   _BIT(6)
/* SDCard clock disable (0) / enable (1) */
#define CLKPWR_MSCARD_SDCARD_EN    _BIT(5)
/* SDCard clock divider = (ARM_PLL clock / n) Hz, n = 1 to 15,
   disabled when n = 0*/
#define CLKPWR_MSCARD_SDCARD_DIV(n) ((n) & 0xF)

/**********************************************************************
* clkpwr_macclk_ctrl register definitions
**********************************************************************/
/* Disables ethernet MAC pins */
#define CLKPWR_MACCTRL_NO_ENET_PIS 0x00
/* Ethernet MAC pins setup for MII */
#define CLKPWR_MACCTRL_USE_MII_PINS 0x08
/* Ethernet MAC pins setup for RMII */
#define CLKPWR_MACCTRL_USE_RMII_PINS 0x18
/* Mask for MAC pins selection */
#define CLKPWR_MACCTRL_PINS_MSK    0x18
/* Ethernet MAC DMA clock disable (0) / enable (1) bit */
#define CLKPWR_MACCTRL_DMACLK_EN   _BIT(2)
/* Ethernet MAC MMIO clock disable (0) / enable (1) bit */
#define CLKPWR_MACCTRL_MMIOCLK_EN  _BIT(1)
/* Ethernet MAC host registers clock disable (0) / enable (1) bit */
#define CLKPWR_MACCTRL_HRCCLK_EN   _BIT(0)

/**********************************************************************
* clkpwr_test_clk_sel register definitions
**********************************************************************/
/* Route PERIPH_CLK to TEST_CLK1 pin */
#define CLKPWR_TESTCLK1_SEL_PERCLK (0x0 << 5)
/* Route RTC to TEST_CLK1 pin */
#define CLKPWR_TESTCLK1_SEL_RTC    (0x1 << 5)
/* Route Main oscillator clock to TEST_CLK1 pin */
#define CLKPWR_TESTCLK1_SEL_MOSC   (0x2 << 5)
/* TEST_CLK1 pin signal selection mask */
#define CLKPWR_TESTCLK1_SEL_MASK   (0x3 << 5)
/* TEST_CLK1 output select, (0) = connected to GPO_00, (1) = use
   selected test 1 clock */
#define CLKPWR_TESTCLK_TESTCLK1_EN _BIT(4)
/* Route PERIPH_CLK to TEST_CLK2 pin */
#define CLKPWR_TESTCLK2_SEL_HCLK   (0x0 << 1)
/* Route PERIPH_CLK to TEST_CLK2 pin */
#define CLKPWR_TESTCLK2_SEL_PERCLK (0x1 << 1)
/* Route USB_CLK to TEST_CLK2 pin */
#define CLKPWR_TESTCLK2_SEL_USBCLK (0x2 << 1)
/* Route Main oscillator clock to TEST_CLK2 pin */
#define CLKPWR_TESTCLK2_SEL_MOSC   (0x5 << 1)
/* Route PLL397 to TEST_CLK2 pin */
#define CLKPWR_TESTCLK2_SEL_PLL397 (0x7 << 1)
/* TEST_CLK2 pin signal selection mask */
#define CLKPWR_TESTCLK2_SEL_MASK   (0x7 << 1)
/* TEST_CLK2 output select, (0) = TEST_CLK2 turned off, (1) = use
   selected test 2 clock */
#define CLKPWR_TESTCLK_TESTCLK2_EN _BIT(0)

/**********************************************************************
* clkpwr_sw_int register definitions
**********************************************************************/
/* Macro for loading the SW interrupt argument value and generating
   and interrupt */
#define CLKPWR_SW_INT(n)           (_BIT(0) | (((n) & 0x7F) << 1))
/* Macro for reading the SW interrupt argument */
#define CLKPWR_SW_GET_ARG(n)       (((n) & 0xFE) >> 1)

/**********************************************************************
* clkpwr_i2c_clk_ctrl register definitions
**********************************************************************/
/* Driver strength for USB_I2C clock and data, (0) = low driver,
   (1) = high drive */
#define CLKPWR_I2CCLK_USBI2CHI_DRIVE _BIT(4)
/* Driver strength for I2C2 clock and data, (0) = low driver,
   (1) = high drive */
#define CLKPWR_I2CCLK_I2C2HI_DRIVE _BIT(3)
/* Driver strength for I2C1 clock and data, (0) = low driver,
   (1) = high drive */
#define CLKPWR_I2CCLK_I2C1HI_DRIVE _BIT(2)
/* Clock enable for I2C2, (0) = disable, (1) = enable */
#define CLKPWR_I2CCLK_I2C2CLK_EN   _BIT(1)
/* Clock enable for I2C1, (0) = disable, (1) = enable */
#define CLKPWR_I2CCLK_I2C1CLK_EN   _BIT(0)

/**********************************************************************
* clkpwr_key_clk_ctrl register definitions
**********************************************************************/
/* Key scanner clock disable (0) / enable (1) bit */
#define CLKPWR_KEYCLKCTRL_CLK_EN   0x1

/**********************************************************************
* clkpwr_adc_clk_ctrl register definitions
**********************************************************************/
/* ADC 32KHz clock disable (0) / enable (1) bit */
#define CLKPWR_ADC32CLKCTRL_CLK_EN 0x1

/**********************************************************************
* clkpwr_pwm_clk_ctrl register definitions
**********************************************************************/
/* PWM2 clock frequency = CLKIN / n, n = 1 to 15, disabled when
   n = 0 */
#define CLKPWR_PWMCLK_PWM2_DIV(n)  (((n) & 0xF) << 8)
/* PWM1 clock frequency = CLKIN / n, n = 1 to 15, disabled when
   n = 0 */
#define CLKPWR_PWMCLK_PWM1_DIV(n)  (((n) & 0xF) << 4)
/* Selects PWM2 clock source, (0) = 32KHz clock, (1) = PERIPH_CLK */
#define CLKPWR_PWMCLK_PWM2SEL_PCLK 0x8
/* Enables PWM2 clock, (0) = disable, (1) = enable */
#define CLKPWR_PWMCLK_PWM2CLK_EN   0x4
/* Selects PWM1 clock source, (0) = 32KHz clock, (1) = PERIPH_CLK */
#define CLKPWR_PWMCLK_PWM1SEL_PCLK 0x2
/* Enables PWM1 clock, (0) = disable, (1) = enable */
#define CLKPWR_PWMCLK_PWM1CLK_EN   0x1

/**********************************************************************
* clkpwr_timer_clk_ctrl register definitions
**********************************************************************/
/* High speed timer clock enable, (0) = disable, (1) = enable */
#define CLKPWR_PWMCLK_HSTIMER_EN   0x2
/* Watchdog timer clock enable, (0) = disable, (1) = enable */
#define CLKPWR_PWMCLK_WDOG_EN      0x1

/**********************************************************************
* clkpwr_timers_pwms_clk_ctrl_1 register definitions
**********************************************************************/
/* Timer 3 clock enable, (0) = disable, (1) = enable */
#define CLKPWR_TMRPWMCLK_TIMER3_EN 0x20
/* Timer 2 clock enable, (0) = disable, (1) = enable */
#define CLKPWR_TMRPWMCLK_TIMER2_EN 0x10
/* Timer 1 clock enable, (0) = disable, (1) = enable */
#define CLKPWR_TMRPWMCLK_TIMER1_EN 0x08
/* Timer 0 clock enable, (0) = disable, (1) = enable */
#define CLKPWR_TMRPWMCLK_TIMER0_EN 0x04
/* PWM 4 clock enable, (0) = disable, (1) = enable */
#define CLKPWR_TMRPWMCLK_PWM4_EN   0x02
/* PWM 3 clock enable, (0) = disable, (1) = enable */
#define CLKPWR_TMRPWMCLK_PWM3_EN   0x01

/**********************************************************************
* clkpwr_spi_clk_ctrl register definitions
**********************************************************************/
/* SPI2 DATIO output level is CLKPWR_SPICLK_USE_SPI2 is 0 */
#define CLKPWR_SPICLK_SET_SPI2DATIO 0x80
/* SPI2 CLK output level is CLKPWR_SPICLK_USE_SPI2 is 0 */
#define CLKPWR_SPICLK_SET_SPI2CLK  0x40
/* SPI2 DATIO and CLK output control, (0) = GPO values in bits 6 and
   7, (1) = controlled by the SPI2 block */
#define CLKPWR_SPICLK_USE_SPI2     0x20
/* SPI2 clock enable, (0) = disable, (1) = enable */
#define CLKPWR_SPICLK_SPI2CLK_EN   0x10
/* SPI1 DATIO output level is CLKPWR_SPICLK_USE_SPI1 is 0 */
#define CLKPWR_SPICLK_SET_SPI1DATIO 0x08
/* SPI1 CLK output level is CLKPWR_SPICLK_USE_SPI1 is 0 */
#define CLKPWR_SPICLK_SET_SPI1CLK  0x04
/* SPI1 DATIO and CLK output control, (0) = GPO values in bits 2 and
   3, (1) = controlled by the SPI1 block */
#define CLKPWR_SPICLK_USE_SPI1     0x02
/* SPI1 clock enable, (0) = disable, (1) = enable */
#define CLKPWR_SPICLK_SPI1CLK_EN   0x01

/**********************************************************************
* clkpwr_nand_clk_ctrl register definitions
**********************************************************************/
/* NAND FLASH controller interrupt select, (0) = SLC, (1) = MLC */
#define CLKPWR_NANDCLK_INTSEL_MLC  0x20
/* Enable DMA_REQ on NAND_RnB for MLC */
#define CLKPWR_NANDCLK_DMA_RNB     0x10
/* Enable DMA_REQ on NAND_INT for MLC */
#define CLKPWR_NANDCLK_DMA_INT     0x08
/* NAND FLASH controller select, (0) = MLC, (1) = SLC */
#define CLKPWR_NANDCLK_SEL_SLC     0x04
/* NAND FLASH MLC clock enable, (0) = disable, (1) = enable */
#define CLKPWR_NANDCLK_MLCCLK_EN   0x02
/* NAND FLASH SLC clock enable, (0) = disable, (1) = enable */
#define CLKPWR_NANDCLK_SLCCLK_EN   0x01

/**********************************************************************
* clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl
* and clkpwr_uart6_clk_ctrl register definitions
**********************************************************************/
/* Macro for loading UART 'Y' divider value */
#define CLKPWR_UART_Y_DIV(y)       ((y) & 0xFF)
/* Macro for loading UART 'X' divider value */
#define CLKPWR_UART_X_DIV(x)       (((x) & 0xFF) << 8)
/* Bit for using HCLK as the UART X/Y divider input, or PERIPH_CLK */
#define CLKPWR_UART_USE_HCLK       _BIT(16)

/**********************************************************************
* clkpwr_irda_clk_ctrl register definitions
**********************************************************************/
/* Macro for loading IRDA 'Y' divider value */
#define CLKPWR_IRDA_Y_DIV(y)       ((y) & 0xFF)
/* Macro for loading IRDA 'X' divider value */
#define CLKPWR_IRDA_X_DIV(x)       (((x) & 0xFF) << 8)

/**********************************************************************
* clkpwr_uart_clk_ctrl register definitions
**********************************************************************/
/* UART6 clock disable (0) / enable (1) bit */
#define CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3)
/* UART5 clock disable (0) / enable (1) bit */
#define CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2)
/* UART4 clock disable (0) / enable (1) bit */
#define CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1)
/* UART3 clock disable (0) / enable (1) bit */
#define CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0)

/**********************************************************************
* clkpwr_dmaclk_ctrl register definitions
**********************************************************************/
/* DMA clock disable (0) / enable (1) bit */
#define CLKPWR_DMACLKCTRL_CLK_EN   0x1

/**********************************************************************
* clkpwr_autoclock register definitions
**********************************************************************/
/* (0) = enable USB autoclock, (1) = always clock */
#define CLKPWR_AUTOCLK_USB_EN      0x40
/* (0) = enable IRAM autoclock, (1) = always clock */
#define CLKPWR_AUTOCLK_IRAM_EN     0x02
/* (0) = enable IROM autoclock, (1) = always clock */
#define CLKPWR_AUTOCLK_IROM_EN     0x01

/* Macro pointing to Clock and Power control registers */
#define CLKPWR ((CLKPWR_REGS_T *)(CLK_PM_BASE))

#ifdef __cplusplus
}
#endif

#endif /* LPC32XX_CLKPWR_H */