lpc32xx_clkpwr.h

NXP LPC3000系列 wince BSP包

/**********************************************************************
* clkpwr_pwr_ctrl register definitions
**********************************************************************/
/* Force HCLK and ARMCLK to run from PERIPH_CLK to save power */
#define CLKPWR_CTRL_FORCE_PCLK      _BIT(10)
/* SDRAM self refresh request */
#define CLKPWR_SDRAM_SELF_RFSH      _BIT(9)
/* Update SDRAM self refresh request */
#define CLKPWR_UPD_SDRAM_SELF_RFSH  _BIT(8)
/* Enable auto exit SDRAM self refresh */
#define CLKPWR_AUTO_SDRAM_SELF_RFSH _BIT(7)
/* Disable HCLK to the USB */
#define CLKPWR_DISABLE_USB_HCLK     _BIT(6)
/* Highcore pin level (when CLKPWR_HIGHCORE_GPIO_EN is set) */
#define CLKPWR_HIGHCORE_STATE_BIT   _BIT(5)
/* SYSCLKEN pin level (when CLKPWR_SYSCLKEN_GPIO_EN is set) */
#define CLKPWR_SYSCLKEN_STATE_BIT   _BIT(4)
/* Enable SYSCLKEN pin as a GPIO bit */
#define CLKPWR_SYSCLKEN_GPIO_EN     _BIT(3)
/* Selects direct run mode (0) or run mode (1) */
#define CLKPWR_SELECT_RUN_MODE      _BIT(2)
/* Enable Highcore pin as a GPIO bit */
#define CLKPWR_HIGHCORE_GPIO_EN     _BIT(1)
/* Enable Highcore pin as a GPIO bit */
#define CLKPWR_STOP_MODE_CTRL       _BIT(0)

/**********************************************************************
* clkpwr_pll397_ctrl register definitions
**********************************************************************/
/* Backup PLL397 lock status mask bit */
#define CLKPWR_PLL397_MSLOCK_STS   _BIT(10)
/* PLL397 bypass enable bit */
#define CLKPWR_PLL397_BYPASS       _BIT(9)
/* PLL397 charge pump biases */
#define CLKPWR_PLL397_BIAS_NORM    0x000 /* Normal charge pump bias */
#define CLKPWR_PLL397_BIAS_N12_5   0x040 /* -12.5% charge pump bias */
#define CLKPWR_PLL397_BIAS_N25     0x080 /* -25% charge pump bias */
#define CLKPWR_PLL397_BIAS_N37_5   0x0C0 /* -37.5% charge pump bias */
#define CLKPWR_PLL397_BIAS_P12_5   0x100 /* 12.5% charge pump bias */
#define CLKPWR_PLL397_BIAS_P25     0x140 /* 25% charge pump bias */
#define CLKPWR_PLL397_BIAS_P37_5   0x180 /* 37.5% charge pump bias */
#define CLKPWR_PLL397_BIAS_P50     0x1C0 /* 50% charge pump bias */
/* PLL397 charge pump bias mask */
#define CLKPWR_PLL397_BIAS_MASK    0x1C0
/* PLL397 enable/disable bit, (0) = enable, (1) = disable */
#define CLKPWR_SYSCTRL_PLL397_DIS  _BIT(1)
/* Read only status mask bit of the PLL397 oscillator lock state,
   (0) = PLL397 is not locked, (1) = PLL397 is locked */
#define CLKPWR_SYSCTRL_PLL397_STS  _BIT(0)

/**********************************************************************
* clkpwr_main_osc_ctrl register definitions
**********************************************************************/
/* Main oscillator load cap adder, adds 0 to 12.7pF, or 0.1pF per
   increment */
#define CLKPWR_MOSC_ADD_CAP(n)      (((n) & 0x7F) << 2)
/* Main oscillator load cap adder bit mask */
#define CLKPWR_MOSC_CAP_MASK        (0x7F << 2)
/* Main oscillator test mode, passes through mode */
#define CLKPWR_TEST_MODE            _BIT(1)
/* Main oscillator disable, power down mode */
#define CLKPWR_MOSC_DISABLE         _BIT(0)

/**********************************************************************
* clkpwr_sysclk_ctrl register definitions
**********************************************************************/
/* Number used by the clock switching circuitry to decide how long a
   bad phase must be present before clock switching is triggered */
#define CLKPWR_SYSCTRL_BP_TRIG(n)   (((n) & 0x3FF) << 2)
/* Mask for bad phase bits */
#define CLKPWR_SYSCTRL_BP_MASK      (0x3FF << 2)
/* (1) = Use main oscillator, (1) = use PLL397 oscillator */
#define CLKPWR_SYSCTRL_USEPLL397    _BIT(1)
/* Read only status mask bit of the select oscillator, (0) = main
   oscillator, (1) = PLL397 oscillator */
#define CLKPWR_SYSCTRL_SYSCLKMUX    _BIT(0)

/**********************************************************************
* clkpwr_lcdclk_ctrl register definitions
**********************************************************************/
/* Muxed pin configuration for TFT display and RGB444 support */
#define CLKPWR_LCDCTRL_LCDTYPE_TFT12 0x000
/* Muxed pin configuration for TFT display and RGB565 support */
#define CLKPWR_LCDCTRL_LCDTYPE_TFT16 0x040
/* Muxed pin configuration for TFT display and RGB1:555 support */
#define CLKPWR_LCDCTRL_LCDTYPE_TFT15 0x080
/* Muxed pin configuration for TFT display and RGB888 support */
#define CLKPWR_LCDCTRL_LCDTYPE_TFT24 0x0C0
/* Muxed pin configuration for STN display and 4-bit mono support */
#define CLKPWR_LCDCTRL_LCDTYPE_STN4M 0x100
/* Muxed pin configuration for STN display and 8-bit mono or color
   support */
#define CLKPWR_LCDCTRL_LCDTYPE_STN8C 0x140
/* Muxed pin configuration for DSTN display and 4-bit mono support */
#define CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 0x180
/* Muxed pin configuration for DSTN display and 8-bit mono or color
   support */
#define CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 0x1C0
/* Mask for LCD panel type */
#define CLKPWR_LCDCTRL_LCDTYPE_MSK 0x01C0
/* LCD clock disable (0) / enable (1) bit */
#define CLKPWR_LCDCTRL_CLK_EN      0x020
/* Macro for setting LCD prescaler, n = 1 to 32 */
#define CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F)
/* Mask for LCD prescaler */
#define CLKPWR_LCDCTRL_PSCALE_MSK  0x001F

/**********************************************************************
* clkpwr_hclkpll_ctrl register definitions
**********************************************************************/
/* Bit to start (1) or stop (0) the main HCLK PLL */
#define CLKPWR_HCLKPLL_POWER_UP    _BIT(16)
/* Main HCLK PLL CCO bypass control (0) = CCO clock to post divider,
   (1) = Bypass CCO and route PLL clock to post divider */
#define CLKPWR_HCLKPLL_CCO_BYPASS  _BIT(15)
/* Main HCLK PLL post divider bypass control (0) = use post divider,
   (1) = Bypass post divider */
#define CLKPWR_HCLKPLL_POSTDIV_BYPASS _BIT(14)
/* Main HCLK PLL feedback divider path control, (0) = feedback
   divider clocked by CCO, (1) = feedback divider clocked by FCLKOUT */
#define CLKPWR_HCLKPLL_FDBK_SEL_FCLK _BIT(13)
/* Main HCLK PLL post divider setting, for a value of n, the divider
   is 2^n, maximum value of n is 3 */
#define CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
/* Main HCLK PLL pre divider setting, for a value of n, the divider
   is (1+n), maximum value of n is 3 */
#define CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
/* Main HCLK PLL feedback setting, for a value of n, the feedback
   is (1+n), maximum value of n is 255 */
#define CLKPWR_HCLKPLL_PLLM(n)     (((n) & 0xFF) << 1)
/* Read only status mask bit of the PLL lock state, (0) = PLL is not
   locked, (1) = PLL is locked */
#define CLKPWR_HCLKPLL_PLL_STS     _BIT(0)

/**********************************************************************
* clkpwr_adc_clk_ctrl_1 register definitions
**********************************************************************/
/* Macro for setting the ADC clock divider when the PERIPH_CLK is
   selected, n = 1 to 256, use 0 to disable */
#define CLKPWR_ADCCTRL1_RTDIV(n)   (((n) & 0xFF) << 0)
/* Clock selection bit for ADC, (0) = RTC, (1) = PERIPH_CLK */
#define CLKPWR_ADCCTRL1_PCLK_SEL   _BIT(8)

/**********************************************************************
* clkpwr_usb_ctrl register definitions
**********************************************************************/
/* USB slave HCLK clock disable (0) / enable (1) bit */
#define CLKPWR_USBCTRL_HCLK_EN     _BIT(24)
/* USB I2C enable, (0) = automatic USB I2C enable, (1) = disable (by
   driving '0' to the OE_TP_N pad */
#define CLKPWR_USBCTRL_USBI2C_EN   _BIT(23)
/* USB_DEV_NEED_CLK enable, (0) = USB_DEV_NEED_CLK not let into clock
   switch, (1) = USB_DEV_NEED_CLK let into clock switch */
#define CLKPWR_USBCTRL_USBDVND_EN  _BIT(22)
/* USB_HOST_NEED_CLK enable, (0) = USB_HOST_NEED_CLK not let into clock
   switch, (1) = USB_HOST_NEED_CLK let into clock switch */
#define CLKPWR_USBCTRL_USBHSTND_EN _BIT(21)
/* USB_DAT_VP and USB_SE0_VM pull-up added to pad */
#define CLKPWR_USBCTRL_PU_ADD      (0x0 << 19)
/* USB_DAT_VP and USB_SE0_VM bus keeper mode */
#define CLKPWR_USBCTRL_BUS_KEEPER  (0x1 << 19)
/* USB_DAT_VP and USB_SE0_VM pull-down added to pad */
#define CLKPWR_USBCTRL_PD_ADD      (0x3 << 19)
/* USB (CLKEN2) clock disable (0) / enable (1) bit */
#define CLKPWR_USBCTRL_CLK_EN2     _BIT(18)
/* USB (CLKEN1) clock disable (0) / enable (1) bit */
#define CLKPWR_USBCTRL_CLK_EN1     _BIT(17)
/* USB PLL Power up (1) / power down (0) bit */
#define CLKPWR_USBCTRL_PLL_PWRUP   _BIT(16)
/* USB PLL CCO bypass bit, (0) = use post divider, (1) = bypass */
#define CLKPWR_USBCTRL_CCO_BYPASS  _BIT(15)
/* USB PLL direct output bit, (0) = use post divider as PLL output,
   (1) = bypass post divider */
#define CLKPWR_USBCTRL_POSTDIV_BYPASS _BIT(14)
/* USB PLL feedback divider path control, (0) = feedback
   divider clocked by CCO, (1) = feedback divider clocked by FCLKOUT */
#define CLKPWR_USBCTRL_FDBK_SEL_FCLK _BIT(13)
/* USB PLL post divider setting, for a value of n, the divider is 2^n,
   maximum value of n is 3 */
#define CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
/* USB PLL pre divider setting, for a value of n, the divider
   is (1+n), maximum value of n is 3 */
#define CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
/* USB PLL feedback setting, for a value of n, the feedback
   is (1+n), maximum value of n is 255 */
#define CLKPWR_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1)
/* Read only status mask bit of the USB PLL lock state, (0) = PLL is
   not locked, (1) = PLL is locked */
#define CLKPWR_USBCTRL_PLL_STS     _BIT(0)

/**********************************************************************
* clkpwr_sdramclk_ctrl register definitions
**********************************************************************/
/* SDRAM RAM_CLK fast slew rate control selection bit */
#define CLKPWR_SDRCLK_FASTSLEW_CLK _BIT(22)
/* SDRAM grouping fast slew rate control selection bit */
#define CLKPWR_SDRCLK_FASTSLEW     _BIT(21)
/* SDRAM data fast slew rate control selection bit */
#define CLKPWR_SDRCLK_FASTSLEW_DAT _BIT(20)
/* SDRAM/DDR controller reset bit */
#define CLKPWR_SDRCLK_SW_DDR_RESET _BIT(19)
/* Select HCLK delay calibration value, n = 0 to 31 at .25nS per tick */
#define CLKPWR_SDRCLK_HCLK_DLY(n)  (((n) & 0x1F) << 14)
/* SDRAM/DDR delay circuitry address status bit */
#define CLKPWR_SDRCLK_DLY_ADDR_STS _BIT(13)
/* Sensitivity factor for DDR SDRAM cal, n = 0 to 7 */
#define CLKPWR_SDRCLK_SENS_FACT(n) (((n) & 0x1F) << 10)
/* Use calibrated settings for DDR SDRAM bit */
#define CLKPWR_SDRCLK_USE_CAL      _BIT(9)
/* Perform a DDR delay calibration bit */
#define CLKPWR_SDRCLK_DO_CAL       _BIT(8)
/* Enable auto DDR cal on RTC tick bit */
#define CLKPWR_SDRCLK_CAL_ON_RTC   _BIT(7)
/* Select DQS input delay value, n = 0 to 31 at .25nS per tick */
#define CLKPWR_SDRCLK_DQS_DLY(n)   (((n) & 0x1F) << 2)
/* Use DDR (1) or SDRAM (0) bit */
#define CLKPWR_SDRCLK_USE_DDR      _BIT(1)
/* SDRAM/DDR clock disable bit */
#define CLKPWR_SDRCLK_CLK_DIS      _BIT(0)

/**********************************************************************
* clkpwr_ssp_blk_ctrl register definitions
**********************************************************************/
/* SSP1 RX DMA selection, (0) = SSP1RX not connected/SPI2 connected,
   (1) = SSP1RX connected/SPI2 not connected */
#define CLKPWR_SSPCTRL_DMA_SSP1RX  _BIT(5)
/* SSP1 TX DMA selection, (0) = SSP1TX not connected/SPI1 connected,
   (1) = SSP1TX connected/SPI1 not connected */
#define CLKPWR_SSPCTRL_DMA_SSP1TX  _BIT(4)
/* SSP0 RX DMA selection, (0) = SSP1RX not connected/SPI2 connected,
   (1) = SSP1RX connected/SPI3 not connected */
#define CLKPWR_SSPCTRL_DMA_SSP0RX  _BIT(2)
/* SSP0 TX DMA selection, (0) = SSP1TX not connected/SPI1 connected,
   (1) = SSP1TX connected/SPI4 not connected */
#define CLKPWR_SSPCTRL_DMA_SSP0TX  _BIT(3)
/* SSP0 clock disable (0) / enable (1) bit */
#define CLKPWR_SSPCTRL_SSPCLK1_EN  _BIT(1)
/* SSP0 clock disable (0) / enable (1) bit */
#define CLKPWR_SSPCTRL_SSPCLK0_EN  _BIT(0)

/**********************************************************************
* clkpwr_i2s_clk_ctrl register definitions
**********************************************************************/
/* I2S1 TX clock mode, (0) = TX clock drives TX timing, (1) = RX clock
   drives TX timing */
#define CLKPWR_I2SCTRL_I2S1_RX_FOR_TX _BIT(6)
/* I2S1 RX clock mode, (0) = RX clock drives RX timing, (1) = TX clock
   drives RX timing */
#define CLKPWR_I2SCTRL_I2S1_TX_FOR_RX _BIT(5)
/* I2S1 DMA muxing, (0) = HS-UAT7 uses DMA, (1) = I2S1 uses DMA */