lpc32xx_clkpwr.h

NXP LPC3000系列 wince BSP包

/***********************************************************************
* $Id:: lpc32xx_clkpwr.h 1101 2008-08-20 22:25:30Z wellsk             $
*
* Project: LPC3250 Clock and Power controller definitions
*
* Description:
*     This file contains the structure definitions and manifest
*     constants for the LPC3250 chip family component:
*         Clock and Power controller
*
***********************************************************************
* Software that is described herein is for illustrative purposes only  
* which provides customers with programming information regarding the  
* products. This software is supplied "AS IS" without any warranties.  
* NXP Semiconductors assumes no responsibility or liability for the 
* use of the software, conveys no license or title under any patent, 
* copyright, or mask work right to the product. NXP Semiconductors 
* reserves the right to make changes in the software without 
* notification. NXP Semiconductors also make no representation or 
* warranty that such application will be suitable for the specified 
* use without further testing or modification. 
**********************************************************************/

#ifndef LPC32XX_CLKPWR_H
#define LPC32XX_CLKPWR_H

#include "lpc_types.h"
#include "lpc32xx_chip.h"

#ifdef __cplusplus
extern "C" {
#endif

/**********************************************************************
* Clock and Power control register structures
**********************************************************************/

/* Clock and Power control module register structures */ 
typedef struct {
	volatile UNS_32 reserved1 [1];
	volatile UNS_32 cklpwr_ahb_master_prio;
	volatile UNS_32 cklpwr_ahb_grant_set;
	volatile UNS_32 cklpwr_ahb_grant_clear;
	volatile UNS_32 cklpwr_ahb_grant_sts;
	volatile UNS_32 clkpwr_bootmap;
	volatile UNS_32 clkpwr_p01_er; /* P0/P1 start enable register */
	volatile UNS_32 clkpwr_usbclk_pdiv;
	volatile UNS_32 clkpwr_int_er; /* Internal start enable register */
	volatile UNS_32 clkpwr_int_rs; /* Internal raw status register */
	volatile UNS_32 clkpwr_int_sr; /* Internal masked status register */
	volatile UNS_32 clkpwr_int_ap; /* Internal active pol register */
	volatile UNS_32 clkpwr_pin_er; /* Pin start enable register */
	volatile UNS_32 clkpwr_pin_rs; /* Pin raw status register */
	volatile UNS_32 clkpwr_pin_sr; /* Pin masked status register */
	volatile UNS_32 clkpwr_pin_ap; /* Pin active polarity register */
	volatile UNS_32 clkpwr_hclk_div;
	volatile UNS_32 clkpwr_pwr_ctrl;
    volatile UNS_32 clkpwr_pll397_ctrl;
	volatile UNS_32 clkpwr_main_osc_ctrl;
	volatile UNS_32 clkpwr_sysclk_ctrl;
    volatile UNS_32 clkpwr_lcdclk_ctrl;
	volatile UNS_32 clkpwr_hclkpll_ctrl;
	volatile UNS_32 reserved2;
	volatile UNS_32 clkpwr_adc_clk_ctrl_1;
	volatile UNS_32 clkpwr_usb_ctrl;
	volatile UNS_32 clkpwr_sdramclk_ctrl;
	volatile UNS_32 clkpwr_ddr_lap_nom;
	volatile UNS_32 clkpwr_ddr_lap_count;
	volatile UNS_32 clkpwr_ddr_cal_delay;
	volatile UNS_32 clkpwr_ssp_blk_ctrl;
	volatile UNS_32 clkpwr_i2s_clk_ctrl;
	volatile UNS_32 clkpwr_ms_ctrl;
	volatile UNS_32 reserved4 [3];
	volatile UNS_32 clkpwr_macclk_ctrl;
	volatile UNS_32 reserved5 [4];
	volatile UNS_32 clkpwr_test_clk_sel;
	volatile UNS_32 clkpwr_sw_int;
	volatile UNS_32 clkpwr_i2c_clk_ctrl;
	volatile UNS_32 clkpwr_key_clk_ctrl;
	volatile UNS_32 clkpwr_adc_clk_ctrl;
	volatile UNS_32 clkpwr_pwm_clk_ctrl;
	volatile UNS_32 clkpwr_timer_clk_ctrl;
	volatile UNS_32 clkpwr_timers_pwms_clk_ctrl_1;
	volatile UNS_32 clkpwr_spi_clk_ctrl;
	volatile UNS_32 clkpwr_nand_clk_ctrl;
	volatile UNS_32 reserved7;
	volatile UNS_32 clkpwr_uart3_clk_ctrl;
	volatile UNS_32 clkpwr_uart4_clk_ctrl;
	volatile UNS_32 clkpwr_uart5_clk_ctrl;
	volatile UNS_32 clkpwr_uart6_clk_ctrl;
	volatile UNS_32 clkpwr_irda_clk_ctrl;
	volatile UNS_32 clkpwr_uart_clk_ctrl;
	volatile UNS_32 clkpwr_dmaclk_ctrl;

	volatile UNS_32 clkpwr_autoclock;
} CLKPWR_REGS_T;

/**********************************************************************
* cklpwr_ahb_master_prio, cklpwr_ahb_grant_set,
* cklpwr_ahb_grant_clear, and cklpwr_ahb_grant_sts register
* definitions
*
* cklpwr_ahb_master_prio
*     A '1' in the selected bit location of this register will enable
*     high bus priority instead of round robin priority.
* cklpwr_ahb_grant_set (write only)
*     A write of '1' to a bit in a selected location will enable a
*     forced grant inactive state for that bus master.
* cklpwr_ahb_grant_clear (write only)
*     A write of '1' to a bit in a selected location will disable a
*     forced grant inactive state for that bus master.
* cklpwr_ahb_grant_sts (read only)
*     A '1' or '0' will indicate that the bis has been cleared in the
*     cklpwr_ahb_grant_set or cklpwr_ahb_grant_clear registers,
*     respectively
**********************************************************************/
/* ARM data master bus bit */
#define CLKPWR_AHB_ARM_DATA        _BIT(0)
/* ARM instruction master bus bit */
#define CLKPWR_AHB_ARM_INST        _BIT(1)
/* ARM DMA master M0 bit */
#define CLKPWR_AHB_DMA_M0          _BIT(2)
/* ARM DMA master M1 bit */
#define CLKPWR_AHB_DMA_M1          _BIT(3)
/* ARM DMA master ethernet bit */
#define CLKPWR_AHB_ETHERNET        _BIT(4)
/* ARM DMA master USB bit */
#define CLKPWR_AHB_USB             _BIT(5)
/* ARM DMA master LCD bit */
#define CLKPWR_AHB_LCD             _BIT(6)

/**********************************************************************
* clkpwr_bootmap register definitions
**********************************************************************/
/* Boot mapping at address 0x0, (0) = IROM, (1) = IRAM */
#define CLKPWR_BOOTMAP_SEL_BIT     0x1

/**********************************************************************
* clkpwr_start_gpio register bit definitions
**********************************************************************/
/* GPI/O sources bit positions for interrupt wakeup */
#define CLKPWR_GPIOSRC_P1IO23_BIT  _BIT(31)
#define CLKPWR_GPIOSRC_P1IO22_BIT  _BIT(30)
#define CLKPWR_GPIOSRC_P1IO21_BIT  _BIT(29)
#define CLKPWR_GPIOSRC_P1IO20_BIT  _BIT(28)
#define CLKPWR_GPIOSRC_P1IO19_BIT  _BIT(27)
#define CLKPWR_GPIOSRC_P1IO18_BIT  _BIT(26)
#define CLKPWR_GPIOSRC_P1IO17_BIT  _BIT(25)
#define CLKPWR_GPIOSRC_P1IO16_BIT  _BIT(24)
#define CLKPWR_GPIOSRC_P1IO15_BIT  _BIT(23)
#define CLKPWR_GPIOSRC_P1IO14_BIT  _BIT(22)
#define CLKPWR_GPIOSRC_P1IO13_BIT  _BIT(21)
#define CLKPWR_GPIOSRC_P1IO12_BIT  _BIT(20)
#define CLKPWR_GPIOSRC_P1IO11_BIT  _BIT(19)
#define CLKPWR_GPIOSRC_P1IO10_BIT  _BIT(18)
#define CLKPWR_GPIOSRC_P1IO9_BIT   _BIT(17)
#define CLKPWR_GPIOSRC_P1IO8_BIT   _BIT(16)
#define CLKPWR_GPIOSRC_P1IO7_BIT   _BIT(15)
#define CLKPWR_GPIOSRC_P1IO6_BIT   _BIT(14)
#define CLKPWR_GPIOSRC_P1IO5_BIT   _BIT(13)
#define CLKPWR_GPIOSRC_P1IO4_BIT   _BIT(12)
#define CLKPWR_GPIOSRC_P1IO3_BIT   _BIT(11)
#define CLKPWR_GPIOSRC_P1IO2_BIT   _BIT(10)
#define CLKPWR_GPIOSRC_P1IO1_BIT   _BIT(9)
#define CLKPWR_GPIOSRC_P1IO0_BIT   _BIT(8)
#define CLKPWR_GPIOSRC_P0IO7_BIT   _BIT(7)
#define CLKPWR_GPIOSRC_P0IO6_BIT   _BIT(6)
#define CLKPWR_GPIOSRC_P0IO5_BIT   _BIT(5)
#define CLKPWR_GPIOSRC_P0IO4_BIT   _BIT(4)
#define CLKPWR_GPIOSRC_P0IO3_BIT   _BIT(3)
#define CLKPWR_GPIOSRC_P0IO2_BIT   _BIT(2)
#define CLKPWR_GPIOSRC_P0IO1_BIT   _BIT(1)
#define CLKPWR_GPIOSRC_P0IO0_BIT   _BIT(0)

/**********************************************************************
* clkpwr_usbclk_pdiv register definitions
**********************************************************************/
/* Macro for setting USB PLL clock predivider */
#define CLKPWR_SET_PLL_USBPDIV(n)  ((n) & 0xF)
/* Mask for USB PLL clock predivider bits */
#define CLKPWR_USBPDIV_PLL_MASK    0xF

/**********************************************************************
* clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int,
* clkpwr_start_pol_int, register bit definitions
**********************************************************************/
/* Internal sources bit positions for interrupt wakeup */
#define CLKPWR_INTSRC_ADC_BIT      _BIT(31)
#define CLKPWR_INTSRC_TS_P_BIT     _BIT(30)
#define CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26)
#define CLKPWR_INTSRC_MSTIMER_BIT  _BIT(25)
#define CLKPWR_INTSRC_RTC_BIT      _BIT(24)
#define CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23)
#define CLKPWR_INTSRC_USB_BIT      _BIT(22)
#define CLKPWR_INTSRC_I2C_BIT      _BIT(21)
#define CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20)
#define CLKPWR_INTSRC_USBATXINT_BIT _BIT(19)
#define CLKPWR_INTSRC_KEY_BIT      _BIT(16)
#define CLKPWR_INTSRC_GPIO_05_BIT  _BIT(5)
#define CLKPWR_INTSRC_GPIO_04_BIT  _BIT(4)
#define CLKPWR_INTSRC_GPIO_03_BIT  _BIT(3)
#define CLKPWR_INTSRC_GPIO_02_BIT  _BIT(2)
#define CLKPWR_INTSRC_GPIO_01_BIT  _BIT(1)
#define CLKPWR_INTSRC_GPIO_00_BIT  _BIT(0)

/**********************************************************************
* clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin,
* clkpwr_start_pol_pin register bit definitions
**********************************************************************/
/* External sources bit positions for interrupt wakeup */
#define CLKPWR_EXTSRC_U7_RX_BIT    _BIT(31)
#define CLKPWR_EXTSRC_U7_HCTS_BIT  _BIT(30)
#define CLKPWR_EXTSRC_U6_IRRX_BIT  _BIT(28)
#define CLKPWR_EXTSRC_U5_RX_BIT    _BIT(26)
#define CLKPWR_EXTSRC_GPI_11_BIT   _BIT(25)
#define CLKPWR_EXTSRC_U3_RX_BIT    _BIT(24)
#define CLKPWR_EXTSRC_U2_HCTS_BIT  _BIT(23)
#define CLKPWR_EXTSRC_U2_RX_BIT    _BIT(22)
#define CLKPWR_EXTSRC_U1_RX_BIT    _BIT(21)
#define CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18)
#define CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17)
#define CLKPWR_EXTSRC_GPIO_O6_BIT  _BIT(16)
#define CLKPWR_EXTSRC_GPIO_O5_BIT  _BIT(15)
#define CLKPWR_EXTSRC_GPIO_O4_BIT  _BIT(14)
#define CLKPWR_EXTSRC_GPIO_O3_BIT  _BIT(13)
#define CLKPWR_EXTSRC_GPIO_O2_BIT  _BIT(12)
#define CLKPWR_EXTSRC_GPIO_O1_BIT  _BIT(11)
#define CLKPWR_EXTSRC_GPIO_O0_BIT  _BIT(10)
#define CLKPWR_EXTSRC_SYSCLKEN_BIT _BIT(9)
#define CLKPWR_EXTSRC_SPI1_DATIN_BIT _BIT(8)
#define CLKPWR_EXTSRC_GPIO_O7_BIT  _BIT(7)
#define CLKPWR_EXTSRC_SPI2_DATIN_BIT _BIT(6)
#define CLKPWR_EXTSRC_GPIO_10_BIT  _BIT(5)
#define CLKPWR_EXTSRC_GPIO_O9_BIT  _BIT(4)
#define CLKPWR_EXTSRC_GPIO_O8_BIT  _BIT(3)

/**********************************************************************
* clkpwr_hclk_div register definitions
**********************************************************************/
/* HCLK Divider DDRAM clock stop (used for SDRAM only) */
#define CLKPWR_HCLKDIV_DDRCLK_STOP (0x0 << 7)
/* HCLK Divider DDRAM clock is the same speed as the ARM */
#define CLKPWR_HCLKDIV_DDRCLK_NORM (0x1 << 7)
/* HCLK Divider DDRAM clock is half the speed as the ARM */
#define CLKPWR_HCLKDIV_DDRCLK_HALF (0x2 << 7)
/* HCLK Divider PERIPH_CLK divider, for a value of n, the divider is
   (1+n), maximum value of n is 32 */
#define CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2)
/* HCLK Divider, for a value of n, the divider is (2^n), maximum
   value of n is 2 for a divider of 4 */
#define CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3)