📄 encoder.c
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#include "encoder.h"
signed long encoder_value=0;//current value of encoder
signed int encoder_overflow=0;
void ConfigIntQEI(unsigned int config)
{
_QEIIF = 0; /* clear Interrupt flag */
_QEIIP = config & 0x07; /* bits <2:0> is the priority*/
_QEIIE = (config & 0x8)>>3; /* bit 3 is interrupt enable/diable */
}
void CloseQEI(void)
{
_QEIIE = 0; /* disable interrupt */
_QEIM = 0x0; /* QEI/Timer off */
_QEIIF = 0; /* clear IF flag */
}
//unsigned int ReadQEI(void)
//{
// return POSCNT; /* return the current position count */
//}
//void WriteQEI(unsigned int position)
//{
// MAXCNT = position; /* set the Maxium Count */
//}
//void OpenQEI(unsigned int config1, unsigned int config2)
//{
/* clear CNTERR bit */
// QEICONbits.CNTERR = 0;
/* configures the QEI/Timer */
// QEICON = config1 & 0x2fff;
// QEICONbits.UPDN = config1 >>11; /* assign up/down */
/* configures the Digital Filters */
// DFLTCON = config2;
//}
void QEI_init(void)
{
CloseQEI();
ADPCFG |= 0x0030;// Configure QEI pins as digital inputs
QEICONbits.QEIM = 0;// Disable QEI Module
ConfigIntQEI(QEI_INT_PRI_1 & QEI_INT_ENABLE);//
//ConfigIntQEI(QEI_INT_DISABLE);// disable interrupt
POSCNT = ENCODER_ZERO_VALUE;//initial value of encoder
MAXCNT = 0xFFFF;//max value of POSCNT
/* configures the QEI/Timer : QEICON*/
QEICONbits.CNTERR = 0;//clear CNTERR bit
QEICONbits.QEISIDL =1;//Stop in Idle Mode
//QEICONbits.INDX : read only output pin
//QEICONbits.UPDN = 1;//1 = Position Counter Direction is positive (+)
//become read only when QEIM=1xx
// with position counter reset by match (MAXCNT)
QEICONbits.SWPAB=0;// Phase A and Phase B Input not swapped
//QEICONbits.PCDOUT=0;//Position Counter Direction State Output is disable
//pin69 UPDN
//be aware of I/O conflict with CN interrupt
//QEICONbits.TQGATE=1;//Timer Gated Time Accumulation is enabled
//QEICONbits.TQCKPS=0b00;//Timer Input Clock Prescale 1:1
//11 = 1:256 prescale value
//10 = 1:64 prescale value
//01 = 1:8 prescale value
//00 = 1:1 prescale value
QEICONbits.POSRES=0;//Position Counter Reset is disabled
//QEICONbits.TQCS=0;//Timer Clock Source Select
//0 = Internal clock TCY
//QEICONbits.UPDN_SRC=0;//Position Counter Direction Selection Control
//0 = Control/Status bit, UPDN (QEICON<11>)
// don't care when QEIM=0b111
/* configures the Digital Filters */
DFLTCONbits.CEID=1;//Count Error Interrupt is Disabled
DFLTCONbits.QEOUT=1;//QEA/QEB Digital Filter Output is Enabled
//DFLTCONbits.QEOUT=0;
DFLTCONbits.QECK=0b011;//QEA/QEB Digital Filter Clock Divide Select
//111 = 1:256 Clock Divide
//110 = 1:128 Clock Divide
//101 = 1:64 Clock Divide
//100 = 1:32 Clock Divide
//011 = 1:16 Clock Divide
//010 = 1:4 Clock Divide
//001 = 1:2 Clock Divide
//000 = 1:1 Clock Divide
//DFLTCONbits.INDOUT=1;//Index Channel Digital Filter Output Enable
//DFLTCONbits.INDCK=0b000;//NDCK<2:0>: Index Channel Digital Filter Clock Divide Select
DFLTCONbits.IMV=0b00;// Index Match Value
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