manqiesite.map.eqn

cpld实现的并行数据串行传输收发模块（类曼切斯特码）。最大2M并行码率。

D1_count_m40[4]_carry_eqn = D1L01;
D1_count_m40[4]_lut_out = D1_count_m40[4] $ (!D1_count_m40[4]_carry_eqn);
D1_count_m40[4] = DFFEAS(D1_count_m40[4]_lut_out, clk_co, !clr_co, , , , , D1L02, );

--D1L21 is in_reg:inst2|count_m40[4]~232
--operation mode is arithmetic

D1L21 = CARRY(D1_count_m40[4] & (!D1L01));


--D1L81 is in_reg:inst2|en_code~179
--operation mode is normal

D1L81 = !D1_count_m40[3] & !D1_count_m40[4];


--D1_shift_reg[0] is in_reg:inst2|shift_reg[0]
--operation mode is normal

D1_shift_reg[0]_lut_out = D1L52 & (D1_shift_reg_tmp[1] & !D1L42) # !D1L52 & data_co[0] & (D1L42);
D1_shift_reg[0] = DFFEAS(D1_shift_reg[0]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_clk2 is in_reg:inst2|clk2
--operation mode is normal

D1_clk2 = D1_i_busy & (!D1_count_m40[0]);


--D1L41 is in_reg:inst2|count_m40[5]~235
--operation mode is normal

D1L41 = !D1_count_m40[0] & !D1_count_m40[1] & !D1_count_m40[2] & !D1_count_m40[4];


--D1L52 is in_reg:inst2|reduce_nor~2
--operation mode is normal

D1L52 = D1_count_m40[5] # D1_count_m40[3] # !D1L41;


--D1L32 is in_reg:inst2|process2~73
--operation mode is normal

D1L32 = D1_count_m40[5] & (D1_count_m40[3] # D1_count_m40[4]);


--D1L61 is in_reg:inst2|d_code~1
--operation mode is normal

D1L61 = D1L52 & !clr_co & !D1L22 & !D1L32;


--B1L52 is code:inst|reduce_nor~0
--operation mode is normal

B1L52 = B1_count_m40[0] & B1_count_m40[1] & B1L62;


--B1_shift_r[1] is code:inst|shift_r[1]
--operation mode is normal

B1_shift_r[1]_lut_out = B1_shift_r[0];
B1_shift_r[1] = DFFEAS(B1_shift_r[1]_lut_out, B1_clk2, !clr_co, , D1_en_code, , , , );


--D1L62 is in_reg:inst2|reduce_nor~13
--operation mode is normal

D1L62 = D1L41 & (!D1_count_m40[3]);


--D1L02 is in_reg:inst2|process0~0
--operation mode is normal

D1L02 = D1_count_m40[5] & D1_count_m40[3] & D1L41 # !D1_i_busy;


--D1_shift_reg_tmp[1] is in_reg:inst2|shift_reg_tmp[1]
--operation mode is normal

D1_shift_reg_tmp[1]_lut_out = D1_shift_reg[1];
D1_shift_reg_tmp[1] = DFFEAS(D1_shift_reg_tmp[1]_lut_out, clk_co, VCC, , , , , , );


--D1L42 is in_reg:inst2|process2~74
--operation mode is normal

D1L42 = D1L22 # D1L32 # !D1L52;


--B1_shift_r[0] is code:inst|shift_r[0]
--operation mode is normal

B1_shift_r[0]_lut_out = D1_d_code;
B1_shift_r[0] = DFFEAS(B1_shift_r[0]_lut_out, B1_clk2, !clr_co, , D1_en_code, , , , );


--D1_shift_reg[1] is in_reg:inst2|shift_reg[1]
--operation mode is normal

D1_shift_reg[1]_lut_out = D1L52 & (D1_shift_reg_tmp[2] & !D1L42) # !D1L52 & data_co[1] & (D1L42);
D1_shift_reg[1] = DFFEAS(D1_shift_reg[1]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[2] is in_reg:inst2|shift_reg_tmp[2]
--operation mode is normal

D1_shift_reg_tmp[2]_lut_out = D1_shift_reg[2];
D1_shift_reg_tmp[2] = DFFEAS(D1_shift_reg_tmp[2]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[2] is in_reg:inst2|shift_reg[2]
--operation mode is normal

D1_shift_reg[2]_lut_out = D1L52 & (D1_shift_reg_tmp[3] & !D1L42) # !D1L52 & data_co[2] & (D1L42);
D1_shift_reg[2] = DFFEAS(D1_shift_reg[2]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[3] is in_reg:inst2|shift_reg_tmp[3]
--operation mode is normal

D1_shift_reg_tmp[3]_lut_out = D1_shift_reg[3];
D1_shift_reg_tmp[3] = DFFEAS(D1_shift_reg_tmp[3]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[3] is in_reg:inst2|shift_reg[3]
--operation mode is normal

D1_shift_reg[3]_lut_out = D1L52 & (D1_shift_reg_tmp[4] & !D1L42) # !D1L52 & data_co[3] & (D1L42);
D1_shift_reg[3] = DFFEAS(D1_shift_reg[3]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[4] is in_reg:inst2|shift_reg_tmp[4]
--operation mode is normal

D1_shift_reg_tmp[4]_lut_out = D1_shift_reg[4];
D1_shift_reg_tmp[4] = DFFEAS(D1_shift_reg_tmp[4]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[4] is in_reg:inst2|shift_reg[4]
--operation mode is normal

D1_shift_reg[4]_lut_out = D1L52 & (D1_shift_reg_tmp[5] & !D1L42) # !D1L52 & data_co[4] & (D1L42);
D1_shift_reg[4] = DFFEAS(D1_shift_reg[4]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[5] is in_reg:inst2|shift_reg_tmp[5]
--operation mode is normal

D1_shift_reg_tmp[5]_lut_out = D1_shift_reg[5];
D1_shift_reg_tmp[5] = DFFEAS(D1_shift_reg_tmp[5]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[5] is in_reg:inst2|shift_reg[5]
--operation mode is normal

D1_shift_reg[5]_lut_out = D1L52 & (D1_shift_reg_tmp[6] & !D1L42) # !D1L52 & data_co[5] & (D1L42);
D1_shift_reg[5] = DFFEAS(D1_shift_reg[5]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[6] is in_reg:inst2|shift_reg_tmp[6]
--operation mode is normal

D1_shift_reg_tmp[6]_lut_out = D1_shift_reg[6];
D1_shift_reg_tmp[6] = DFFEAS(D1_shift_reg_tmp[6]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[6] is in_reg:inst2|shift_reg[6]
--operation mode is normal

D1_shift_reg[6]_lut_out = D1L52 & (D1_shift_reg_tmp[7] & !D1L42) # !D1L52 & data_co[6] & (D1L42);
D1_shift_reg[6] = DFFEAS(D1_shift_reg[6]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[7] is in_reg:inst2|shift_reg_tmp[7]
--operation mode is normal

D1_shift_reg_tmp[7]_lut_out = D1_shift_reg[7];
D1_shift_reg_tmp[7] = DFFEAS(D1_shift_reg_tmp[7]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[7] is in_reg:inst2|shift_reg[7]
--operation mode is normal

D1_shift_reg[7]_lut_out = D1L52 & (D1_shift_reg_tmp[8] & !D1L42) # !D1L52 & data_co[7] & (D1L42);
D1_shift_reg[7] = DFFEAS(D1_shift_reg[7]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[8] is in_reg:inst2|shift_reg_tmp[8]
--operation mode is normal

D1_shift_reg_tmp[8]_lut_out = D1_shift_reg[8];
D1_shift_reg_tmp[8] = DFFEAS(D1_shift_reg_tmp[8]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[8] is in_reg:inst2|shift_reg[8]
--operation mode is normal

D1_shift_reg[8]_lut_out = D1L52 & (D1_shift_reg_tmp[9] & !D1L42) # !D1L52 & data_co[8] & (D1L42);
D1_shift_reg[8] = DFFEAS(D1_shift_reg[8]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[9] is in_reg:inst2|shift_reg_tmp[9]
--operation mode is normal

D1_shift_reg_tmp[9]_lut_out = D1_shift_reg[9];
D1_shift_reg_tmp[9] = DFFEAS(D1_shift_reg_tmp[9]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[9] is in_reg:inst2|shift_reg[9]
--operation mode is normal

D1_shift_reg[9]_lut_out = D1L52 & (D1_shift_reg_tmp[10] & !D1L42) # !D1L52 & data_co[9] & (D1L42);
D1_shift_reg[9] = DFFEAS(D1_shift_reg[9]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[10] is in_reg:inst2|shift_reg_tmp[10]
--operation mode is normal

D1_shift_reg_tmp[10]_lut_out = D1_shift_reg[10];
D1_shift_reg_tmp[10] = DFFEAS(D1_shift_reg_tmp[10]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[10] is in_reg:inst2|shift_reg[10]
--operation mode is normal

D1_shift_reg[10]_lut_out = D1L52 & (D1_shift_reg_tmp[11] & !D1L42) # !D1L52 & data_co[10] & (D1L42);
D1_shift_reg[10] = DFFEAS(D1_shift_reg[10]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[11] is in_reg:inst2|shift_reg_tmp[11]
--operation mode is normal

D1_shift_reg_tmp[11]_lut_out = D1_shift_reg[11];
D1_shift_reg_tmp[11] = DFFEAS(D1_shift_reg_tmp[11]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[11] is in_reg:inst2|shift_reg[11]
--operation mode is normal

D1_shift_reg[11]_lut_out = D1L52 & (D1_shift_reg_tmp[12] & !D1L42) # !D1L52 & data_co[11] & (D1L42);
D1_shift_reg[11] = DFFEAS(D1_shift_reg[11]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[12] is in_reg:inst2|shift_reg_tmp[12]
--operation mode is normal

D1_shift_reg_tmp[12]_lut_out = D1_shift_reg[12];
D1_shift_reg_tmp[12] = DFFEAS(D1_shift_reg_tmp[12]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[12] is in_reg:inst2|shift_reg[12]
--operation mode is normal

D1_shift_reg[12]_lut_out = D1L52 & (D1_shift_reg_tmp[13] & !D1L42) # !D1L52 & data_co[12] & (D1L42);
D1_shift_reg[12] = DFFEAS(D1_shift_reg[12]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[13] is in_reg:inst2|shift_reg_tmp[13]
--operation mode is normal

D1_shift_reg_tmp[13]_lut_out = D1_shift_reg[13];
D1_shift_reg_tmp[13] = DFFEAS(D1_shift_reg_tmp[13]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[13] is in_reg:inst2|shift_reg[13]
--operation mode is normal

D1_shift_reg[13]_lut_out = D1L52 & (D1_shift_reg_tmp[14] & !D1L42) # !D1L52 & data_co[13] & (D1L42);
D1_shift_reg[13] = DFFEAS(D1_shift_reg[13]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[14] is in_reg:inst2|shift_reg_tmp[14]
--operation mode is normal

D1_shift_reg_tmp[14]_lut_out = D1_shift_reg[14];
D1_shift_reg_tmp[14] = DFFEAS(D1_shift_reg_tmp[14]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[14] is in_reg:inst2|shift_reg[14]
--operation mode is normal

D1_shift_reg[14]_lut_out = D1L52 & (D1_shift_reg_tmp[15] & !D1L42) # !D1L52 & data_co[14] & (D1L42);
D1_shift_reg[14] = DFFEAS(D1_shift_reg[14]_lut_out, D1_clk2, !clr_co, , , , , , );


--D1_shift_reg_tmp[15] is in_reg:inst2|shift_reg_tmp[15]
--operation mode is normal

D1_shift_reg_tmp[15]_lut_out = D1_shift_reg[15];
D1_shift_reg_tmp[15] = DFFEAS(D1_shift_reg_tmp[15]_lut_out, clk_co, VCC, , , , , , );


--D1_shift_reg[15] is in_reg:inst2|shift_reg[15]
--operation mode is normal

D1_shift_reg[15]_lut_out = D1L41 & data_co[15] & !D1_count_m40[5] & !D1_count_m40[3];
D1_shift_reg[15] = DFFEAS(D1_shift_reg[15]_lut_out, D1_clk2, !clr_co, , , , , , );


--C1L03 is deco_t:inst1|jo~0
--operation mode is normal

C1L03 = C1_clk_key & !C1_count_t[2] & C1L33;


--x8_clk is x8_clk
--operation mode is input

x8_clk = INPUT();


--clk_co is clk_co
--operation mode is input

clk_co = INPUT();


--clr_co is clr_co
--operation mode is input

clr_co = INPUT();


--en_co is en_co
--operation mode is input

en_co = INPUT();


--wr_co is wr_co
--operation mode is input

wr_co = INPUT();


--decode_en is decode_en
--operation mode is input

decode_en = INPUT();


--data_co[0] is data_co[0]
--operation mode is input

data_co[0] = INPUT();


--data_co[1] is data_co[1]
--operation mode is input

data_co[1] = INPUT();


--data_co[2] is data_co[2]
--operation mode is input

data_co[2] = INPUT();


--data_co[3] is data_co[3]
--operation mode is input

data_co[3] = INPUT();


--data_co[4] is data_co[4]
--operation mode is input

data_co[4] = INPUT();


--data_co[5] is data_co[5]
--operation mode is input

data_co[5] = INPUT();


--data_co[6] is data_co[6]
--operation mode is input

data_co[6] = INPUT();


--data_co[7] is data_co[7]
--operation mode is input

data_co[7] = INPUT();


--data_co[8] is data_co[8]
--operation mode is input

data_co[8] = INPUT();


--data_co[9] is data_co[9]
--operation mode is input

data_co[9] = INPUT();


--data_co[10] is data_co[10]
--operation mode is input

data_co[10] = INPUT();


--data_co[11] is data_co[11]
--operation mode is input

data_co[11] = INPUT();


--data_co[12] is data_co[12]
--operation mode is input

data_co[12] = INPUT();


--data_co[13] is data_co[13]
--operation mode is input

data_co[13] = INPUT();


--data_co[14] is data_co[14]
--operation mode is input

data_co[14] = INPUT();


--data_co[15] is data_co[15]
--operation mode is input

data_co[15] = INPUT();


--q is q
--operation mode is output

q = OUTPUT(C1_q);


--fail is fail
--operation mode is output

fail = OUTPUT(!C1L82);


--ready is ready
--operation mode is output

ready = OUTPUT(C1_ready);


--jo is jo
--operation mode is output

jo = OUTPUT(C1_jo_o);


--code_q is code_q
--operation mode is output

code_q = OUTPUT(B1_q);


--in_busy is in_busy
--operation mode is output

in_busy = OUTPUT(D1_i_busy);


--shift_q is shift_q
--operation mode is output

shift_q = OUTPUT(D1_d_code);