manqiesite.pin

cpld实现的并行数据串行传输收发模块（类曼切斯特码）。最大2M并行码率。

 -- Copyright (C) 1991-2005 Altera Corporation
 -- Your use of Altera Corporation's design tools, logic functions 
 -- and other software and tools, and its AMPP partner logic       
 -- functions, and any output files any of the foregoing           
 -- (including device programming or simulation files), and any    
 -- associated documentation or information are expressly subject  
 -- to the terms and conditions of the Altera Program License      
 -- Subscription Agreement, Altera MegaCore Function License       
 -- Agreement, or other applicable license agreement, including,   
 -- without limitation, that your use is for the sole purpose of   
 -- programming logic devices manufactured by Altera and sold by   
 -- Altera or its authorized distributors.  Please refer to the    
 -- applicable agreement for further details.
 -- 
 -- This is a Quartus II output file. It is for reporting purposes only, and is
 -- not intended for use as a Quartus II input file. This file cannot be used
 -- to make Quartus II pin assignments - for instructions on how to make pin
 -- assignments, please see Quartus II help.
 ---------------------------------------------------------------------------------



 ---------------------------------------------------------------------------------
 -- NC            : No Connect. This pin has no internal connection to the device.
 -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (3.3V).
 -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
 --                 of its bank.
 --					Bank 1:		3.3V
 --					Bank 2:		3.3V
 -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
 --					It can also be used to report unused dedicated pins. The connection
 --					on the board for unused dedicated pins depends on whether this will
 --					be used in a future design. One example is device migration. When
 --					using device migration, refer to the device pin-tables. If it is a
 --					GND pin in the pin table or if it will not be used in a future design
 --					for another purpose the it MUST be connected to GND. If it is an unused
 --					dedicated pin, then it can be connected to a valid signal on the board
 --					(low, high, or toggling) if that signal is required for a different
 --					revision of the design.
 -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
 --					This pin should be connected to GND. It may also be connected  to a
 --					valid signal  on the board  (low, high, or toggling)  if that signal
 --					is required for a different revision of the design.
 -- GND*          : Unused  I/O  pin.   This pin can either be left unconnected or
 --           	    connected to GND.  Connecting this pin to GND will improve the
 --           	    device's immunity to noise.
 -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
 -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
 ---------------------------------------------------------------------------------

Quartus II Version 5.0 Build 148 04/26/2005 SJ Full Version
CHIP  "manqiesite"  ASSIGNED TO AN: EPM570F256C3

Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
-------------------------------------------------------------------------------------------------------------
GNDIO                        : A1        : gnd    :                   :         :           :                
RESERVED_INPUT               : A2        :        :                   :         : 2         :                
VCCIO2                       : A3        : power  :                   : 3.3V    : 2         :                
fail                         : A4        : output : LVTTL             :         : 2         : N              
ready                        : A5        : output : LVTTL             :         : 2         : N              
code_q                       : A6        : output : LVTTL             :         : 2         : N              
RESERVED_INPUT               : A7        :        :                   :         : 2         :                
data_co[5]                   : A8        : input  : LVTTL             :         : 2         : N              
data_co[3]                   : A9        : input  : LVTTL             :         : 2         : N              
en_co                        : A10       : input  : LVTTL             :         : 2         : N              
RESERVED_INPUT               : A11       :        :                   :         : 2         :                
RESERVED_INPUT               : A12       :        :                   :         : 2         :                
RESERVED_INPUT               : A13       :        :                   :         : 2         :                
VCCIO2                       : A14       : power  :                   : 3.3V    : 2         :                
RESERVED_INPUT               : A15       :        :                   :         : 2         :                
GNDIO                        : A16       : gnd    :                   :         :           :                
RESERVED_INPUT               : B1        :        :                   :         : 2         :                
GNDIO                        : B2        : gnd    :                   :         :           :                
RESERVED_INPUT               : B3        :        :                   :         : 2         :                
q                            : B4        : output : LVTTL             :         : 2         : N              
data_co[1]                   : B5        : input  : LVTTL             :         : 2         : N              
clr_co                       : B6        : input  : LVTTL             :         : 2         : N              
RESERVED_INPUT               : B7        :        :                   :         : 2         :                
data_co[0]                   : B8        : input  : LVTTL             :         : 2         : N              
data_co[4]                   : B9        : input  : LVTTL             :         : 2         : N              
RESERVED_INPUT               : B10       :        :                   :         : 2         :                
RESERVED_INPUT               : B11       :        :                   :         : 2         :                
RESERVED_INPUT               : B12       :        :                   :         : 2         :                
RESERVED_INPUT               : B13       :        :                   :         : 2         :                
RESERVED_INPUT               : B14       :        :                   :         : 2         :                
GNDIO                        : B15       : gnd    :                   :         :           :                
RESERVED_INPUT               : B16       :        :                   :         : 2         :                
VCCIO1                       : C1        : power  :                   : 3.3V    : 1         :                
RESERVED_INPUT               : C2        :        :                   :         : 1         :                
RESERVED_INPUT               : C3        :        :                   :         : 1         :                
RESERVED_INPUT               : C4        :        :                   :         : 2         :                
decode_en                    : C5        : input  : LVTTL             :         : 2         : N              
shift_q                      : C6        : output : LVTTL             :         : 2         : N              
data_co[2]                   : C7        : input  : LVTTL             :         : 2         : N              
wr_co                        : C8        : input  : LVTTL             :         : 2         : N              
RESERVED_INPUT               : C9        :        :                   :         : 2         :                
in_busy                      : C10       : output : LVTTL             :         : 2         : N              
RESERVED_INPUT               : C11       :        :                   :         : 2         :                
RESERVED_INPUT               : C12       :        :                   :         : 2         :                
RESERVED_INPUT               : C13       :        :                   :         : 2         :                
RESERVED_INPUT               : C14       :        :                   :         : 2         :                
RESERVED_INPUT               : C15       :        :                   :         : 2         :                
VCCIO2                       : C16       : power  :                   : 3.3V    : 2         :                
RESERVED_INPUT               : D1        :        :                   :         : 1         :