div4.vhd

来自「cpld实现的并行数据串行传输收发模块（类曼切斯特码）。最大2M并行码率。」· VHDL 代码 · 共 33 行

Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

ENTITY div4 IS
	PORT(clr:in std_logic;
	en  :in	 std_logic;
	clk :in  std_logic;
	q :out std_logic
	);
END div4;

ARCHITECTURE div4 of div4 is

signal count:std_logic_vector(1 downto 0);
begin
process(clk,en,clr)
begin
	if(clr='1')then
		count<="00";
	elsif(clk'event and clk='1')then
		if(count="11" )then
			count<="00";
		else
			count<=count+'1';
		end if;
	end if;
end process;

q<=not(count(0));

end div4;