manqiesite.tan.qmsg

cpld实现的并行数据串行传输收发模块（类曼切斯特码）。最大2M并行码率。

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk_co 70 " "Warning: Circuit may not operate. Detected 70 non-operational path(s) clocked by clock \"clk_co\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "in_reg:inst2\|shift_reg_tmp\[1\] in_reg:inst2\|shift_reg\[0\] clk_co 2.843 ns " "Info: Found hold time violation between source  pin or register \"in_reg:inst2\|shift_reg_tmp\[1\]\" and destination pin or register \"in_reg:inst2\|shift_reg\[0\]\" for clock \"clk_co\" (Hold time is 2.843 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.871 ns + Largest " "Info: + Largest clock skew is 3.871 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_co destination 6.173 ns + Longest register " "Info: + Longest clock path from clock \"clk_co\" to destination register is 6.173 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk_co 1 CLK PIN_H5 31 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_H5; Fanout = 31; CLK Node = 'clk_co'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "" { clk_co } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/work/cpld/manqiesite2_final/main.bdf" { { 216 -352 -184 232 "clk_co" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.809 ns) 2.537 ns in_reg:inst2\|i_busy 2 REG LC_X8_Y6_N8 7 " "Info: 2: + IC(1.001 ns) + CELL(0.809 ns) = 2.537 ns; Loc. = LC_X8_Y6_N8; Fanout = 7; REG Node = 'in_reg:inst2\|i_busy'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "1.810 ns" { clk_co in_reg:inst2|i_busy } "NODE_NAME" } "" } } { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.319 ns) 3.746 ns in_reg:inst2\|clk2 3 COMB LC_X9_Y6_N0 17 " "Info: 3: + IC(0.890 ns) + CELL(0.319 ns) = 3.746 ns; Loc. = LC_X9_Y6_N0; Fanout = 17; COMB Node = 'in_reg:inst2\|clk2'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "1.209 ns" { in_reg:inst2|i_busy in_reg:inst2|clk2 } "NODE_NAME" } "" } } { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.853 ns) + CELL(0.574 ns) 6.173 ns in_reg:inst2\|shift_reg\[0\] 4 REG LC_X6_Y7_N5 1 " "Info: 4: + IC(1.853 ns) + CELL(0.574 ns) = 6.173 ns; Loc. = LC_X6_Y7_N5; Fanout = 1; REG Node = 'in_reg:inst2\|shift_reg\[0\]'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "2.427 ns" { in_reg:inst2|clk2 in_reg:inst2|shift_reg[0] } "NODE_NAME" } "" } } { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.429 ns 39.35 % " "Info: Total cell delay = 2.429 ns ( 39.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.744 ns 60.65 % " "Info: Total interconnect delay = 3.744 ns ( 60.65 % )" {  } {  } 0}  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "6.173 ns" { clk_co in_reg:inst2|i_busy in_reg:inst2|clk2 in_reg:inst2|shift_reg[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.173 ns" { clk_co clk_co~combout in_reg:inst2|i_busy in_reg:inst2|clk2 in_reg:inst2|shift_reg[0] } { 0.0ns 0.0ns 1.001ns 0.89ns 1.853ns } { 0.0ns 0.727ns 0.809ns 0.319ns 0.574ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_co source 2.302 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_co\" to source register is 2.302 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk_co 1 CLK PIN_H5 31 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_H5; Fanout = 31; CLK Node = 'clk_co'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "" { clk_co } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/work/cpld/manqiesite2_final/main.bdf" { { 216 -352 -184 232 "clk_co" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.574 ns) 2.302 ns in_reg:inst2\|shift_reg_tmp\[1\] 2 REG LC_X6_Y7_N2 1 " "Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.302 ns; Loc. = LC_X6_Y7_N2; Fanout = 1; REG Node = 'in_reg:inst2\|shift_reg_tmp\[1\]'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "1.575 ns" { clk_co in_reg:inst2|shift_reg_tmp[1] } "NODE_NAME" } "" } } { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns 56.52 % " "Info: Total cell delay = 1.301 ns ( 56.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.001 ns 43.48 % " "Info: Total interconnect delay = 1.001 ns ( 43.48 % )" {  } {  } 0}  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "2.302 ns" { clk_co in_reg:inst2|shift_reg_tmp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.302 ns" { clk_co clk_co~combout in_reg:inst2|shift_reg_tmp[1] } { 0.0ns 0.0ns 1.001ns } { 0.0ns 0.727ns 0.574ns } } }  } 0}  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "6.173 ns" { clk_co in_reg:inst2|i_busy in_reg:inst2|clk2 in_reg:inst2|shift_reg[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.173 ns" { clk_co clk_co~combout in_reg:inst2|i_busy in_reg:inst2|clk2 in_reg:inst2|shift_reg[0] } { 0.0ns 0.0ns 1.001ns 0.89ns 1.853ns } { 0.0ns 0.727ns 0.809ns 0.319ns 0.574ns } } } { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "2.302 ns" { clk_co in_reg:inst2|shift_reg_tmp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.302 ns" { clk_co clk_co~combout in_reg:inst2|shift_reg_tmp[1] } { 0.0ns 0.0ns 1.001ns } { 0.0ns 0.727ns 0.574ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns - " "Info: - Micro clock to output delay of source is 0.235 ns" {  } { { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.931 ns - Shortest register register " "Info: - Shortest register to register delay is 0.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns in_reg:inst2\|shift_reg_tmp\[1\] 1 REG LC_X6_Y7_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y7_N2; Fanout = 1; REG Node = 'in_reg:inst2\|shift_reg_tmp\[1\]'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "" { in_reg:inst2|shift_reg_tmp[1] } "NODE_NAME" } "" } } { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.369 ns) 0.931 ns in_reg:inst2\|shift_reg\[0\] 2 REG LC_X6_Y7_N5 1 " "Info: 2: + IC(0.562 ns) + CELL(0.369 ns) = 0.931 ns; Loc. = LC_X6_Y7_N5; Fanout = 1; REG Node = 'in_reg:inst2\|shift_reg\[0\]'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "0.931 ns" { in_reg:inst2|shift_reg_tmp[1] in_reg:inst2|shift_reg[0] } "NODE_NAME" } "" } } { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.369 ns 39.63 % " "Info: Total cell delay = 0.369 ns ( 39.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.562 ns 60.37 % " "Info: Total interconnect delay = 0.562 ns ( 60.37 % )" {  } {  } 0}  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "0.931 ns" { in_reg:inst2|shift_reg_tmp[1] in_reg:inst2|shift_reg[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.931 ns" { in_reg:inst2|shift_reg_tmp[1] in_reg:inst2|shift_reg[0] } { 0.0ns 0.562ns } { 0.0ns 0.369ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.138 ns + " "Info: + Micro hold delay of destination is 0.138 ns" {  } { { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 20 -1 0 } }  } 0}  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "6.173 ns" { clk_co in_reg:inst2|i_busy in_reg:inst2|clk2 in_reg:inst2|shift_reg[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.173 ns" { clk_co clk_co~combout in_reg:inst2|i_busy in_reg:inst2|clk2 in_reg:inst2|shift_reg[0] } { 0.0ns 0.0ns 1.001ns 0.89ns 1.853ns } { 0.0ns 0.727ns 0.809ns 0.319ns 0.574ns } } } { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "2.302 ns" { clk_co in_reg:inst2|shift_reg_tmp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.302 ns" { clk_co clk_co~combout in_reg:inst2|shift_reg_tmp[1] } { 0.0ns 0.0ns 1.001ns } { 0.0ns 0.727ns 0.574ns } } } { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "0.931 ns" { in_reg:inst2|shift_reg_tmp[1] in_reg:inst2|shift_reg[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.931 ns" { in_reg:inst2|shift_reg_tmp[1] in_reg:inst2|shift_reg[0] } { 0.0ns 0.562ns } { 0.0ns 0.369ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "code:inst\|q clr_co clk_co 2.098 ns register " "Info: tsu for register \"code:inst\|q\" (data pin = \"clr_co\", clock pin = \"clk_co\") is 2.098 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.192 ns + Longest pin register " "Info: + Longest pin to register delay is 4.192 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns clr_co 1 PIN PIN_B6 49 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_B6; Fanout = 49; PIN Node = 'clr_co'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "" { clr_co } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/work/cpld/manqiesite2_final/main.bdf" { { 248 -352 -184 264 "clr_co" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.384 ns) + CELL(1.100 ns) 4.192 ns code:inst\|q 2 REG LC_X5_Y6_N3 5 " "Info: 2: + IC(2.384 ns) + CELL(1.100 ns) = 4.192 ns; Loc. = LC_X5_Y6_N3; Fanout = 5; REG Node = 'code:inst\|q'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "3.484 ns" { clr_co code:inst|q } "NODE_NAME" } "" } } { "code.vhd" "" { Text "E:/work/cpld/manqiesite2_final/code.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.808 ns 43.13 % " "Info: Total cell delay = 1.808 ns ( 43.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.384 ns 56.87 % " "Info: Total interconnect delay = 2.384 ns ( 56.87 % )" {  } {  } 0}  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "4.192 ns" { clr_co code:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.192 ns" { clr_co clr_co~combout code:inst|q } { 0.000ns 0.000ns 2.384ns } { 0.000ns 0.708ns 1.100ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.208 ns + " "Info: + Micro setup delay of destination is 0.208 ns" {  } { { "code.vhd" "" { Text "E:/work/cpld/manqiesite2_final/code.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_co destination 2.302 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_co\" to destination register is 2.302 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk_co 1 CLK PIN_H5 31 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_H5; Fanout = 31; CLK Node = 'clk_co'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "" { clk_co } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/work/cpld/manqiesite2_final/main.bdf" { { 216 -352 -184 232 "clk_co" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.574 ns) 2.302 ns code:inst\|q 2 REG LC_X5_Y6_N3 5 " "Info: 2: + IC(1.001 ns) + CELL(0.574 ns) = 2.302 ns; Loc. = LC_X5_Y6_N3; Fanout = 5; REG Node = 'code:inst\|q'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "1.575 ns" { clk_co code:inst|q } "NODE_NAME" } "" } } { "code.vhd" "" { Text "E:/work/cpld/manqiesite2_final/code.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns 56.52 % " "Info: Total cell delay = 1.301 ns ( 56.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.001 ns 43.48 % " "Info: Total interconnect delay = 1.001 ns ( 43.48 % )" {  } {  } 0}  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "2.302 ns" { clk_co code:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.302 ns" { clk_co clk_co~combout code:inst|q } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } }  } 0}  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "4.192 ns" { clr_co code:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.192 ns" { clr_co clr_co~combout code:inst|q } { 0.000ns 0.000ns 2.384ns } { 0.000ns 0.708ns 1.100ns } } } { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "2.302 ns" { clk_co code:inst|q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.302 ns" { clk_co clk_co~combout code:inst|q } { 0.000ns 0.000ns 1.001ns } { 0.000ns 0.727ns 0.574ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "x8_clk fail deco_t:inst1\|jo_o 10.119 ns register " "Info: tco from clock \"x8_clk\" to destination pin \"fail\" through register \"deco_t:inst1\|jo_o\" is 10.119 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "x8_clk source 7.045 ns + Longest register " "Info: + Longest clock path from clock \"x8_clk\" to source register is 7.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns x8_clk 1 CLK PIN_J5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_J5; Fanout = 5; CLK Node = 'x8_clk'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "" { x8_clk } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/work/cpld/manqiesite2_final/main.bdf" { { -64 264 432 -48 "x8_clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.809 ns) 2.537 ns deco_t:inst1\|count_t\[1\] 2 REG LC_X3_Y7_N9 4 " "Info: 2: + IC(1.001 ns) + CELL(0.809 ns) = 2.537 ns; Loc. = LC_X3_Y7_N9; Fanout = 4; REG Node = 'deco_t:inst1\|count_t\[1\]'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "1.810 ns" { x8_clk deco_t:inst1|count_t[1] } "NODE_NAME" } "" } } { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.555 ns) + CELL(0.125 ns) 4.217 ns deco_t:inst1\|clk1~0 3 COMB LC_X8_Y7_N2 7 " "Info: 3: + IC(1.555 ns) + CELL(0.125 ns) = 4.217 ns; Loc. = LC_X8_Y7_N2; Fanout = 7; COMB Node = 'deco_t:inst1\|clk1~0'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "1.680 ns" { deco_t:inst1|count_t[1] deco_t:inst1|clk1~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.254 ns) + CELL(0.574 ns) 7.045 ns deco_t:inst1\|jo_o 4 REG LC_X3_Y7_N3 2 " "Info: 4: + IC(2.254 ns) + CELL(0.574 ns) = 7.045 ns; Loc. = LC_X3_Y7_N3; Fanout = 2; REG Node = 'deco_t:inst1\|jo_o'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "2.828 ns" { deco_t:inst1|clk1~0 deco_t:inst1|jo_o } "NODE_NAME" } "" } } { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.235 ns 31.72 % " "Info: Total cell delay = 2.235 ns ( 31.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.810 ns 68.28 % " "Info: Total interconnect delay = 4.810 ns ( 68.28 % )" {  } {  } 0}  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "7.045 ns" { x8_clk deco_t:inst1|count_t[1] deco_t:inst1|clk1~0 deco_t:inst1|jo_o } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.045 ns" { x8_clk x8_clk~combout deco_t:inst1|count_t[1] deco_t:inst1|clk1~0 deco_t:inst1|jo_o } { 0.000ns 0.000ns 1.001ns 1.555ns 2.254ns } { 0.000ns 0.727ns 0.809ns 0.125ns 0.574ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.839 ns + Longest register pin " "Info: + Longest register to pin delay is 2.839 ns" { { "Info" "ITDB_N