manqiesite.tan.qmsg

cpld实现的并行数据串行传输收发模块（类曼切斯特码）。最大2M并行码率。

{ "Warning" "WDAT_PRELIMINARY_TIMING" "EPM570F256C3 " "Warning: Timing characteristics of device EPM570F256C3 are preliminary" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "x8_clk " "Info: Assuming node \"x8_clk\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/work/cpld/manqiesite2_final/main.bdf" { { -64 264 432 -48 "x8_clk" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "x8_clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_co " "Info: Assuming node \"clk_co\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/work/cpld/manqiesite2_final/main.bdf" { { 216 -352 -184 232 "clk_co" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_co" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "9 " "Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "in_reg:inst2\|count_m40\[0\] " "Info: Detected ripple clock \"in_reg:inst2\|count_m40\[0\]\" as buffer" {  } { { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "in_reg:inst2\|count_m40\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "code:inst\|clk2 " "Info: Detected ripple clock \"code:inst\|clk2\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "code:inst\|clk2" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "in_reg:inst2\|clk2 " "Info: Detected gated clock \"in_reg:inst2\|clk2\" as buffer" {  } { { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 21 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "in_reg:inst2\|clk2" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "in_reg:inst2\|i_busy " "Info: Detected ripple clock \"in_reg:inst2\|i_busy\" as buffer" {  } { { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 11 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "in_reg:inst2\|i_busy" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "deco_t:inst1\|count_t\[1\] " "Info: Detected ripple clock \"deco_t:inst1\|count_t\[1\]\" as buffer" {  } { { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 27 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "deco_t:inst1\|count_t\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "deco_t:inst1\|count_t\[2\] " "Info: Detected ripple clock \"deco_t:inst1\|count_t\[2\]\" as buffer" {  } { { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 27 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "deco_t:inst1\|count_t\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "deco_t:inst1\|clk_key " "Info: Detected ripple clock \"deco_t:inst1\|clk_key\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "deco_t:inst1\|clk_key" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "deco_t:inst1\|clk1~0 " "Info: Detected gated clock \"deco_t:inst1\|clk1~0\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "deco_t:inst1\|clk1~0" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "deco_t:inst1\|clk2~0 " "Info: Detected gated clock \"deco_t:inst1\|clk2~0\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "deco_t:inst1\|clk2~0" } } } }  } 0}  } {  } 0}