manqiesite.map.qmsg

cpld实现的并行数据串行传输收发模块（类曼切斯特码）。最大2M并行码率。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 10 14:31:24 2009 " "Info: Processing started: Tue Mar 10 14:31:24 2009" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off manqiesite -c manqiesite " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off manqiesite -c manqiesite" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "code.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file code.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 code-code " "Info: Found design unit 1: code-code" {  } { { "code.vhd" "" { Text "E:/work/cpld/manqiesite2_final/code.vhd" 18 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 code " "Info: Found entity 1: code" {  } { { "code.vhd" "" { Text "E:/work/cpld/manqiesite2_final/code.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decode.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decode.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decode-decode " "Info: Found design unit 1: decode-decode" {  } { { "decode.vhd" "" { Text "E:/work/cpld/manqiesite2_final/decode.vhd" 20 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 decode " "Info: Found entity 1: decode" {  } { { "decode.vhd" "" { Text "E:/work/cpld/manqiesite2_final/decode.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "deco_t.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file deco_t.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 deco_t-deco_t " "Info: Found design unit 1: deco_t-deco_t" {  } { { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 23 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 deco_t " "Info: Found entity 1: deco_t" {  } { { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "time.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file time.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 time " "Info: Found entity 1: time" {  } { { "time.bdf" "" { Schematic "E:/work/cpld/manqiesite2_final/time.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div4-div4 " "Info: Found design unit 1: div4-div4" {  } { { "div4.vhd" "" { Text "E:/work/cpld/manqiesite2_final/div4.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 div4 " "Info: Found entity 1: div4" {  } { { "div4.vhd" "" { Text "E:/work/cpld/manqiesite2_final/div4.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shift.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shift.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift " "Info: Found entity 1: shift" {  } { { "shift.bdf" "" { Schematic "E:/work/cpld/manqiesite2_final/shift.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file main.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 main " "Info: Found entity 1: main" {  } { { "main.bdf" "" { Schematic "E:/work/cpld/manqiesite2_final/main.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "in_reg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file in_reg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 in_reg-in_reg " "Info: Found design unit 1: in_reg-in_reg" {  } { { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 18 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 in_reg " "Info: Found entity 1: in_reg" {  } { { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "main " "Info: Elaborating entity \"main\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "deco_t deco_t:inst1 " "Info: Elaborating entity \"deco_t\" for hierarchy \"deco_t:inst1\"" {  } { { "main.bdf" "inst1" { Schematic "E:/work/cpld/manqiesite2_final/main.bdf" { { 160 480 632 384 "inst1" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "jo_count deco_t.vhd(24) " "Info: (10035) Verilog HDL or VHDL information at deco_t.vhd(24): object \"jo_count\" declared but not used" {  } { { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count_m17 deco_t.vhd(118) " "Warning: VHDL Process Statement warning at deco_t.vhd(118): signal \"count_m17\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count_m17 deco_t.vhd(139) " "Warning: VHDL Process Statement warning at deco_t.vhd(139): signal \"count_m17\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "jo deco_t.vhd(140) " "Warning: VHDL Process Statement warning at deco_t.vhd(140): signal \"jo\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "deco deco_t.vhd(140) " "Warning: VHDL Process Statement warning at deco_t.vhd(140): signal \"deco\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 140 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "code code:inst " "Info: Elaborating entity \"code\" for hierarchy \"code:inst\"" {  } { { "main.bdf" "inst" { Schematic "E:/work/cpld/manqiesite2_final/main.bdf" { { 208 168 296 336 "inst" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "clk_count code.vhd(19) " "Info: (10035) Verilog HDL or VHDL information at code.vhd(19): object \"clk_count\" declared but not used" {  } { { "code.vhd" "" { Text "E:/work/cpld/manqiesite2_final/code.vhd" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mo code.vhd(105) " "Warning: VHDL Process Statement warning at code.vhd(105): signal \"mo\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "code.vhd" "" { Text "E:/work/cpld/manqiesite2_final/code.vhd" 105 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "in_reg in_reg:inst2 " "Info: Elaborating entity \"in_reg\" for hierarchy \"in_reg:inst2\"" {  } { { "main.bdf" "inst2" { Schematic "E:/work/cpld/manqiesite2_final/main.bdf" { { 192 -136 24 320 "inst2" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "in_reg:inst2\|shift_reg\[16\] data_in GND " "Warning: Reduced register \"in_reg:inst2\|shift_reg\[16\]\" with stuck data_in port to stuck value GND" {  } { { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 20 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "in_reg:inst2\|shift_reg_tmp\[16\] data_in GND " "Warning: Reduced register \"in_reg:inst2\|shift_reg_tmp\[16\]\" with stuck data_in port to stuck value GND" {  } { { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 20 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "133 " "Info: Implemented 133 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "22 " "Info: Implemented 22 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "104 " "Info: Implemented 104 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 10 14:31:27 2009 " "Info: Processing ended: Tue Mar 10 14:31:27 2009" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}