manqiesite.fit.qmsg

cpld实现的并行数据串行传输收发模块（类曼切斯特码）。最大2M并行码率。

{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 2 76 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  76 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 82 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  82 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.403 ns register pin " "Info: Estimated most critical path is register to pin delay of 3.403 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns deco_t:inst1\|jo_o 1 REG LAB_X3_Y7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y7; Fanout = 2; REG Node = 'deco_t:inst1\|jo_o'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "" { deco_t:inst1|jo_o } "NODE_NAME" } "" } } { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.125 ns) 0.850 ns deco_t:inst1\|fail~0 2 COMB LAB_X3_Y7 2 " "Info: 2: + IC(0.725 ns) + CELL(0.125 ns) = 0.850 ns; Loc. = LAB_X3_Y7; Fanout = 2; COMB Node = 'deco_t:inst1\|fail~0'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "0.850 ns" { deco_t:inst1|jo_o deco_t:inst1|fail~0 } "NODE_NAME" } "" } } { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.168 ns) + CELL(0.571 ns) 1.589 ns deco_t:inst1\|fail~95 3 COMB LAB_X3_Y7 1 " "Info: 3: + IC(0.168 ns) + CELL(0.571 ns) = 1.589 ns; Loc. = LAB_X3_Y7; Fanout = 1; COMB Node = 'deco_t:inst1\|fail~95'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "0.739 ns" { deco_t:inst1|fail~0 deco_t:inst1|fail~95 } "NODE_NAME" } "" } } { "deco_t.vhd" "" { Text "E:/work/cpld/manqiesite2_final/deco_t.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(1.454 ns) 3.403 ns fail 4 PIN PIN_A4 0 " "Info: 4: + IC(0.360 ns) + CELL(1.454 ns) = 3.403 ns; Loc. = PIN_A4; Fanout = 0; PIN Node = 'fail'" {  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "1.814 ns" { deco_t:inst1|fail~95 fail } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/work/cpld/manqiesite2_final/main.bdf" { { 200 632 808 216 "fail" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.150 ns 63.18 % " "Info: Total cell delay = 2.150 ns ( 63.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.253 ns 36.82 % " "Info: Total interconnect delay = 1.253 ns ( 36.82 % )" {  } {  } 0}  } { { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "3.403 ns" { deco_t:inst1|jo_o deco_t:inst1|fail~0 deco_t:inst1|fail~95 fail } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and/or routability requirements required full optimization" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 10 14:31:30 2009 " "Info: Processing ended: Tue Mar 10 14:31:30 2009" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}