manqiesite.fit.qmsg

cpld实现的并行数据串行传输收发模块（类曼切斯特码）。最大2M并行码率。

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "x8_clk Global clock in PIN J5 " "Info: Automatically promoted signal \"x8_clk\" to use Global clock in PIN J5" {  } { { "main.bdf" "" { Schematic "E:/work/cpld/manqiesite2_final/main.bdf" { { -64 264 432 -48 "x8_clk" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "in_reg:inst2\|clk2 Global clock " "Info: Automatically promoted signal \"in_reg:inst2\|clk2\" to use Global clock" {  } { { "in_reg.vhd" "" { Text "E:/work/cpld/manqiesite2_final/in_reg.vhd" 21 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "deco_t:inst1\|clk1~0 Global clock " "Info: Automatically promoted signal \"deco_t:inst1\|clk1~0\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "deco_t:inst1\|clk1~0" } } } } { "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" "" { Report "E:/work/cpld/manqiesite2_final/db/manqiesite_cmp.qrpt" Compiler "manqiesite" "UNKNOWN" "V1" "E:/work/cpld/manqiesite2_final/db/manqiesite.quartus_db" { Floorplan "E:/work/cpld/manqiesite2_final/" "" "" { deco_t:inst1|clk1~0 } "NODE_NAME" } "" } } { "E:/work/cpld/manqiesite2_final/manqiesite.fld" "" { Floorplan "E:/work/cpld/manqiesite2_final/manqiesite.fld" "" "" { deco_t:inst1|clk1~0 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "27 unused 3.30 20 7 0 " "Info: Number of I/O pins in group: 27 (unused VREF, 3.30 VCCIO, 20 input, 7 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}