📄 decode.vhd
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Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
ENTITY decode IS
PORT(clr:in std_logic;
en :in std_logic;
clk :in std_logic;
d :in std_logic;
q :out std_logic;
fail:out std_logic;
ready:out std_logic; --数据准备好
clk1x:out std_logic;
clk2x:out std_logic;
deco_o:out std_logic;
jo_o :out std_logic
);
END decode;
ARCHITECTURE decode of decode is
SIGNAL clk1,clk2,count_t,den,deco,jo,jo_count:std_logic;
SIGNAL chk_r :std_logic_vector(3 downto 0);
SIGNAL count_m17:std_logic_vector(4 downto 0);
begin
------------------分频器-------------------
process(clk,en,clr)
begin
if(clr='1') then
count_t<='1';
elsif(clk'event and clk='1')then
if(count_t='1')then
count_t<='0';
elsif(en='1')then
count_t<='1';
end if;
end if;
end process;
clk2<=count_t;
clk1<=not(not(clk and '1'));
clk1x<=clk1;
clk2x<=clk2;
------------------M17---------------------
process(clk2,den,clr) ---2同步码+16数据+1奇偶+(1空闲)
begin
if(clr='1') then
count_m17<="00000";
elsif(clk2'event and clk2='1')then
if(count_m17="10000" )then
count_m17<="00000";
elsif(den='1')then
count_m17<=count_m17+'1';
end if;
end if;
end process;
-----------------同步码检测器--------------
process(clk1,clk2,en,clr,d)
begin
if(clr='1' or count_m17="10000")then
chk_r<="0000";
elsif(clk1'event and clk1='1')then
if(en='1')then
chk_r<=chk_r(2 downto 0)&d;
end if;
end if;
if(count_m17="10000" or clr='1')then
den<='0';
elsif(clk2'event and clk2='1')then
if(chk_r="1100")then --同步成功
den<='1';
end if;
end if;
end process;
----------------解码、奇偶校验-------------
process(clk1,clk2,den,d)
begin
if(den='1')then
deco<=not(clk2 xor d); --解码
else
deco<='0';
end if;
if(clk1'event and clk1='1')then
if(count_m17<="0111" and den='1')then --奇偶校验
if(jo_count='1')then --每隔一个clk1采样一次
jo_count<='0';
else
jo<=jo xor deco;
jo_count<='1';
end if;
else
jo_count<='0';
end if;
end if;
if(clk1'event and clk1='1')then
if(count_m17<="01111" and den='1')then --选择输出,消毛刺
q<=deco;
else
q<='0';
end if;
end if;
--奇偶校验输出
if(count_m17 ="10000")then
fail<= jo xor deco;
else
fail<= '0';
end if;
if(clk1'event and clk1='1')then --ready信号输出,延迟1clk1
ready<=den;
end if;
end process;
deco_o<=deco;
jo_o <=jo;
end decode;
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