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cpld实现的并行数据串行传输收发模块（类曼切斯特码）。最大2M并行码率。

Library IEEE;
USE IEEE.STD_logic_1164.all;
USE IEEE.STD_logic_unsigned.all;

ENTITY code IS
	PORT(en:in std_logic;
	d  :in std_logic;
	clk:in std_logic;
	clr:in std_logic;
	q  :out std_logic
	);
END code;

ARCHITECTURE code OF code IS
SIGNAL clk_count   :std_logic_vector(1 downto 0);
SIGNAL clk1,clk2,jo,mo:std_logic;
SIGNAL count_m40   :std_logic_vector(5 downto 0);
SIGNAL shift_r     :std_logic_vector(2 downto 0);

begin
----------------分频器--------------------------
process(clk)
begin
	if(clk'event and clk='1')then
		if(clk_count="11" or clr='1')then
			clk_count<="00";
		elsif(en='1')then
			clk_count<=clk_count +'1';
		end if;	
	end if;
end process;

clk1<=clk;
clk2<=clk_count(0);


---------------M40计数器----------------------

process(clk1,en,clr)
begin
	if(clr='1')then
		count_m40<=(others=>'0');
	elsif(clk1'event and clk='1')then
		if(count_m40="100111")then       --0-39 40次
			count_m40<=(others=>'0');
		elsif(en='1')then
			count_m40<=count_m40+'1';
		end if;
	end if;
end process;

------------------三位移位寄存器---------------

process(clk2,en,clr)
begin
	if(clr='1')then
		shift_r<=(others=>'0');
	elsif(clk2'event and clk2='1')then
		if(en='1')then
			shift_r<=shift_r(1 downto 0)&d;
		end if;
	end if;
end process;

-----------------奇偶校验器-----------------------

process(clk2,en,clr,count_m40)
begin
	if(clr='1')then
		jo<='0';
	elsif(clk2'event and clk2='1')then
		if(en='1')then
			if(count_m40>="000000" and count_m40<="000101")then  --0-5
				jo<='0';	--清零
			elsif(count_m40>="000110" and count_m40<="100101")then --6-37
				jo<=jo xor shift_r(2);
			end if;
		end if;
	end if;
end process;

--------------------编码器-------------------------

process(clk1,clk2,en,clr,count_m40,jo,shift_r)
begin
	if(count_m40>="000000" and count_m40<="000010")then  --0-2
		mo<='1';
	elsif(count_m40>="000011" and count_m40<="000101")then --3-5
		mo<='0';
	elsif(count_m40>="000110" and count_m40<="100101")then --6-37
		mo<=NOT(shift_r(2) xor clk2);
	elsif(count_m40>="100110" and count_m40<="100111")then --38-39
		mo<=NOT(jo xor clk2);
	end if;
	
	if(clr='1')then    --D触发器消除毛刺
	elsif(clk1'event and clk1='1')then
		if(en='1')then
			q<=mo;
		end if;
	end if;
end process;

END ARCHITECTURE;