in_reg.vhd

来自「cpld实现的并行数据串行传输收发模块（类曼切斯特码）。最大2M并行码率。」· VHDL 代码 · 共 96 行

Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

ENTITY in_reg is
port(clk	:in  std_logic;
	en		:in  std_logic;
	clr		:in  std_logic;
	data_in :in  std_logic_vector(15 downto 0);
	wr		:in  std_logic;
	i_busy	:out std_logic;
	en_code :out std_logic;
	d_code	:out std_logic
);

end in_reg;

ARCHITECTURE in_reg of in_reg is
signal count_m40:std_logic_vector(5 downto 0);
signal shift_reg,shift_reg_tmp:std_logic_vector(16 downto 0);
signal active,clk2:std_logic;    --active:0 don't work  1 work
begin



-------------M40+1--------------------- control by active ; clk ; 0-39
process(clk,en,clr,active) 
begin
	if(clr='1')then
		count_m40<="000000";
	elsif(clk'event and clk='1')then
		if(count_m40="101000" or active='0')then  --39+1 or don't work
			count_m40<="000000";
		elsif(active='1')then
			count_m40<=count_m40+ '1';
		end if;
	end if;
end process;
clk2<=active and not(count_m40(0));

--------------active(busy)----------------- control by wr  count_m40; clk;  wr:1->active:1  count_m40:39-> active:0
process(clk,en,clr)
begin
	if(clr='1')then
		active<='0';
	elsif(clk'event and clk='1')then
		if(count_m40="100111")then
			active<='0';
		elsif(wr='1' and en='1')then
			active<='1';
		else
			active<=active;
		end if;
	end if;
end process;

i_busy<=active;
--------------shift------------------- control by active m40 clk2; 0:lock  1-38:shift
process(clk,clk2,active,clr,count_m40)
begin
	if(clk'event and clk='1')then
		shift_reg_tmp<=shift_reg;
	end if;
	
	if(clr='1')then
		shift_reg<=(others=>'0');	
	elsif(clk2'event and clk2='1')then
		if(count_m40="000000")then        
			shift_reg<='0'&data_in; 
		elsif(count_m40>="000001" and count_m40<="100110")then
			d_code<=shift_reg(0);
			shift_reg(15 downto 0)<=shift_reg_tmp(16 downto 1);
		else
			shift_reg<=(others=>'0');
		end if;
	end if;
	

end process;


--------------code_en -------------------  control by m40 clk2;  m40:1-39 ->en:1  m40:
process(clk,clk2,clr,count_m40)
begin
	if(clr='1')then
		en_code <='0';
	elsif(clk'event and clk='1')then
		if(count_m40="000000")then
			en_code  <='0';
		elsif(count_m40>="000001" and count_m40<="100111")then
			en_code  <='1';
		end if;
	end  if;
end process;

end in_reg;