manqiesite.map.rpt

cpld实现的并行数据串行传输收发模块（类曼切斯特码）。最大2M并行码率。

+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 104     ;
; Total combinational functions     ; 79      ;
;     -- Total 4-input functions    ; 38      ;
;     -- Total 3-input functions    ; 10      ;
;     -- Total 2-input functions    ; 17      ;
;     -- Total 1-input functions    ; 14      ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 69      ;
; Total logic cells in carry chains ; 17      ;
; I/O pins                          ; 29      ;
; Maximum fan-out node              ; clr_co  ;
; Maximum fan-out                   ; 49      ;
; Total fan-out                     ; 419     ;
; Average fan-out                   ; 3.15    ;
+-----------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                      ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |main                      ; 104 (0)     ; 69           ; 0          ; 29   ; 0            ; 35 (0)       ; 25 (0)            ; 44 (0)           ; 17 (0)          ; |main               ;
;    |code:inst|             ; 23 (23)     ; 12           ; 0          ; 0    ; 0            ; 11 (11)      ; 3 (3)             ; 9 (9)            ; 6 (6)           ; |main|code:inst     ;
;    |deco_t:inst1|          ; 30 (30)     ; 17           ; 0          ; 0    ; 0            ; 13 (13)      ; 6 (6)             ; 11 (11)          ; 5 (5)           ; |main|deco_t:inst1  ;
;    |in_reg:inst2|          ; 51 (51)     ; 40           ; 0          ; 0    ; 0            ; 11 (11)      ; 16 (16)           ; 24 (24)          ; 6 (6)           ; |main|in_reg:inst2  ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 69    ;
; Number of registers using Synchronous Clear  ; 19    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 44    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 11    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; 3:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; Yes        ; |main|in_reg:inst2|shift_reg[13] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/work/cpld/manqiesite2_final/manqiesite.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Mar 10 14:31:24 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off manqiesite -c manqiesite
Info: Found 2 design units, including 1 entities, in source file code.vhd
    Info: Found design unit 1: code-code
    Info: Found entity 1: code
Info: Found 2 design units, including 1 entities, in source file decode.vhd
    Info: Found design unit 1: decode-decode
    Info: Found entity 1: decode
Info: Found 2 design units, including 1 entities, in source file deco_t.vhd
    Info: Found design unit 1: deco_t-deco_t
    Info: Found entity 1: deco_t
Info: Found 1 design units, including 1 entities, in source file time.bdf
    Info: Found entity 1: time
Info: Found 2 design units, including 1 entities, in source file div4.vhd
    Info: Found design unit 1: div4-div4
    Info: Found entity 1: div4
Info: Found 1 design units, including 1 entities, in source file shift.bdf
    Info: Found entity 1: shift
Info: Found 1 design units, including 1 entities, in source file main.bdf
    Info: Found entity 1: main
Info: Found 2 design units, including 1 entities, in source file in_reg.vhd
    Info: Found design unit 1: in_reg-in_reg
    Info: Found entity 1: in_reg
Info: Elaborating entity "main" for the top level hierarchy
Info: Elaborating entity "deco_t" for hierarchy "deco_t:inst1"
Info: (10035) Verilog HDL or VHDL information at deco_t.vhd(24): object "jo_count" declared but not used
Warning: VHDL Process Statement warning at deco_t.vhd(118): signal "count_m17" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at deco_t.vhd(139): signal "count_m17" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at deco_t.vhd(140): signal "jo" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at deco_t.vhd(140): signal "deco" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "code" for hierarchy "code:inst"
Info: (10035) Verilog HDL or VHDL information at code.vhd(19): object "clk_count" declared but not used
Warning: VHDL Process Statement warning at code.vhd(105): signal "mo" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "in_reg" for hierarchy "in_reg:inst2"
Warning: Reduced register "in_reg:inst2|shift_reg[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "in_reg:inst2|shift_reg_tmp[16]" with stuck data_in port to stuck value GND
Info: Implemented 133 device resources after synthesis - the final resource count might be different
    Info: Implemented 22 input pins
    Info: Implemented 7 output pins
    Info: Implemented 104 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
    Info: Processing ended: Tue Mar 10 14:31:27 2009
    Info: Elapsed time: 00:00:03