manqiesite.tan.rpt

cpld实现的并行数据串行传输收发模块（类曼切斯特码）。最大2M并行码率。

; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; x8_clk          ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; clk_co          ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'x8_clk'                                                                                                                                                                                                      ;
+-------+------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                      ; To                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 145.07 MHz ( period = 6.893 ns )               ; deco_t:inst1|chk_r[0]     ; deco_t:inst1|den          ; x8_clk     ; x8_clk   ; None                        ; None                      ; 1.707 ns                ;
; N/A   ; 147.28 MHz ( period = 6.790 ns )               ; deco_t:inst1|chk_r[2]     ; deco_t:inst1|den          ; x8_clk     ; x8_clk   ; None                        ; None                      ; 1.604 ns                ;
; N/A   ; 154.75 MHz ( period = 6.462 ns )               ; deco_t:inst1|chk_r[1]     ; deco_t:inst1|den          ; x8_clk     ; x8_clk   ; None                        ; None                      ; 1.276 ns                ;
; N/A   ; 163.45 MHz ( period = 6.118 ns )               ; deco_t:inst1|chk_r[3]     ; deco_t:inst1|den          ; x8_clk     ; x8_clk   ; None                        ; None                      ; 0.932 ns                ;
; N/A   ; 178.67 MHz ( period = 5.597 ns )               ; deco_t:inst1|count_m17[2] ; deco_t:inst1|den          ; x8_clk     ; x8_clk   ; None                        ; None                      ; 2.755 ns                ;
; N/A   ; 178.70 MHz ( period = 5.596 ns )               ; deco_t:inst1|count_m17[2] ; deco_t:inst1|clk_key      ; x8_clk     ; x8_clk   ; None                        ; None                      ; 2.754 ns                ;
; N/A   ; 185.87 MHz ( period = 5.380 ns )               ; deco_t:inst1|count_m17[3] ; deco_t:inst1|den          ; x8_clk     ; x8_clk   ; None                        ; None                      ; 2.538 ns                ;
; N/A   ; 185.91 MHz ( period = 5.379 ns )               ; deco_t:inst1|count_m17[3] ; deco_t:inst1|clk_key      ; x8_clk     ; x8_clk   ; None                        ; None                      ; 2.537 ns                ;
; N/A   ; 192.34 MHz ( period = 5.199 ns )               ; deco_t:inst1|count_m17[0] ; deco_t:inst1|den          ; x8_clk     ; x8_clk   ; None                        ; None                      ; 2.357 ns                ;
; N/A   ; 192.38 MHz ( period = 5.198 ns )               ; deco_t:inst1|count_m17[0] ; deco_t:inst1|clk_key      ; x8_clk     ; x8_clk   ; None                        ; None                      ; 2.356 ns                ;
; N/A   ; 195.62 MHz ( period = 5.112 ns )               ; deco_t:inst1|count_m17[1] ; deco_t:inst1|den          ; x8_clk     ; x8_clk   ; None                        ; None                      ; 2.270 ns                ;
; N/A   ; 195.66 MHz ( period = 5.111 ns )               ; deco_t:inst1|count_m17[1] ; deco_t:inst1|clk_key      ; x8_clk     ; x8_clk   ; None                        ; None                      ; 2.269 ns                ;
; N/A   ; 200.80 MHz ( period = 4.980 ns )               ; deco_t:inst1|count_m17[4] ; deco_t:inst1|den          ; x8_clk     ; x8_clk   ; None                        ; None                      ; 2.138 ns                ;
; N/A   ; 200.84 MHz ( period = 4.979 ns )               ; deco_t:inst1|count_m17[4] ; deco_t:inst1|clk_key      ; x8_clk     ; x8_clk   ; None                        ; None                      ; 2.137 ns                ;
; N/A   ; 233.97 MHz ( period = 4.274 ns )               ; deco_t:inst1|count_m17[2] ; deco_t:inst1|jo_o         ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.875 ns                ;
; N/A   ; 239.46 MHz ( period = 4.176 ns )               ; deco_t:inst1|count_m17[2] ; deco_t:inst1|count_m17[3] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.543 ns                ;
; N/A   ; 239.46 MHz ( period = 4.176 ns )               ; deco_t:inst1|count_m17[2] ; deco_t:inst1|count_m17[2] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.543 ns                ;
; N/A   ; 239.46 MHz ( period = 4.176 ns )               ; deco_t:inst1|count_m17[2] ; deco_t:inst1|count_m17[4] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.543 ns                ;
; N/A   ; 239.46 MHz ( period = 4.176 ns )               ; deco_t:inst1|count_m17[2] ; deco_t:inst1|count_m17[1] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.543 ns                ;
; N/A   ; 239.46 MHz ( period = 4.176 ns )               ; deco_t:inst1|count_m17[2] ; deco_t:inst1|count_m17[0] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.543 ns                ;
; N/A   ; 242.25 MHz ( period = 4.128 ns )               ; deco_t:inst1|count_m17[1] ; deco_t:inst1|jo_o         ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.802 ns                ;
; N/A   ; 252.59 MHz ( period = 3.959 ns )               ; deco_t:inst1|count_m17[3] ; deco_t:inst1|count_m17[3] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.326 ns                ;
; N/A   ; 252.59 MHz ( period = 3.959 ns )               ; deco_t:inst1|count_m17[3] ; deco_t:inst1|count_m17[2] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.326 ns                ;
; N/A   ; 252.59 MHz ( period = 3.959 ns )               ; deco_t:inst1|count_m17[3] ; deco_t:inst1|count_m17[4] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.326 ns                ;
; N/A   ; 252.59 MHz ( period = 3.959 ns )               ; deco_t:inst1|count_m17[3] ; deco_t:inst1|count_m17[1] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.326 ns                ;
; N/A   ; 252.59 MHz ( period = 3.959 ns )               ; deco_t:inst1|count_m17[3] ; deco_t:inst1|count_m17[0] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.326 ns                ;
; N/A   ; 264.69 MHz ( period = 3.778 ns )               ; deco_t:inst1|count_m17[0] ; deco_t:inst1|count_m17[3] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.145 ns                ;
; N/A   ; 264.69 MHz ( period = 3.778 ns )               ; deco_t:inst1|count_m17[0] ; deco_t:inst1|count_m17[2] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.145 ns                ;
; N/A   ; 264.69 MHz ( period = 3.778 ns )               ; deco_t:inst1|count_m17[0] ; deco_t:inst1|count_m17[4] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.145 ns                ;
; N/A   ; 264.69 MHz ( period = 3.778 ns )               ; deco_t:inst1|count_m17[0] ; deco_t:inst1|count_m17[1] ; x8_clk     ; x8_clk   ; None                        ; None                      ; 3.145 ns                ;