manqiesite.tan.rpt

cpld实现的并行数据串行传输收发模块（类曼切斯特码）。最大2M并行码率。

Timing Analyzer report for manqiesite
Tue Mar 10 14:31:34 2009
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'x8_clk'
  6. Clock Setup: 'clk_co'
  7. Clock Hold: 'x8_clk'
  8. Clock Hold: 'clk_co'
  9. tsu
 10. tco
 11. th
 12. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------+-------------------------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From                          ; To                            ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------+-------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 2.098 ns                         ; clr_co                        ; code:inst|q                   ;            ; clk_co   ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 10.119 ns                        ; deco_t:inst1|jo_o             ; fail                          ; x8_clk     ;          ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 3.533 ns                         ; decode_en                     ; deco_t:inst1|chk_r[3]         ;            ; x8_clk   ; 0            ;
; Clock Setup: 'x8_clk'        ; N/A                                      ; None          ; 145.07 MHz ( period = 6.893 ns ) ; deco_t:inst1|chk_r[0]         ; deco_t:inst1|den              ; x8_clk     ; x8_clk   ; 0            ;
; Clock Setup: 'clk_co'        ; N/A                                      ; None          ; 190.44 MHz ( period = 5.251 ns ) ; in_reg:inst2|shift_reg[3]     ; in_reg:inst2|shift_reg_tmp[3] ; clk_co     ; clk_co   ; 0            ;
; Clock Hold: 'x8_clk'         ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; deco_t:inst1|den              ; deco_t:inst1|ready            ; x8_clk     ; x8_clk   ; 18           ;
; Clock Hold: 'clk_co'         ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; in_reg:inst2|shift_reg_tmp[1] ; in_reg:inst2|shift_reg[0]     ; clk_co     ; clk_co   ; 70           ;
; Total number of failed paths ;                                          ;               ;                                  ;                               ;                               ;            ;          ; 88           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------+-------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM570F256C3       ;      ;    ;             ;