📄 sfr_r81b.inc
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ilvl1_cmp0ic .btequ 1,cmp0ic ;
ilvl2_cmp0ic .btequ 2,cmp0ic ;
ir_cmp0ic .btequ 3,cmp0ic ; Interrupt request bit
;
int0ic .equ 005dh ; INT0 interrupt control register
ilvl0_int0ic .btequ 0,int0ic ; Interrupt priority level select bit
ilvl1_int0ic .btequ 1,int0ic ;
ilvl2_int0ic .btequ 2,int0ic ;
ir_int0ic .btequ 3,int0ic ; Interrupt request bit
pol_int0ic .btequ 4,int0ic ; Polarity select bit
;
;-------------------------------------------------------
; Timer Z mode register
;-------------------------------------------------------
tyzmr .equ 0080h
tzmr .equ 0080h
;
tzmod0 .btequ 4,tzmr ; Timer Z operation mode bit
tzmod1 .btequ 5,tzmr ;
tzwc .btequ 6,tzmr ; Timer Z write control bit
tzs .btequ 7,tzmr ; Timer Z count start flag
;
;-------------------------------------------------------
; Timer Z waveform output control register
;-------------------------------------------------------
pum .equ 0084h
;
tzopl .btequ 5,pum ; Timer Z output level latch
inostg .btequ 6,pum ; INT0 pin one-shot trigger control bit
inoseg .btequ 7,pum ; INT0 pin one-shot trigger polarity select bit
;
;-------------------------------------------------------
; Timer Z registers
;-------------------------------------------------------
prez .equ 0085h ; Prescaler Z register
;
tzsc .equ 0086h ; Timer Z secondary register
;
tzpr .equ 0087h ; Timer Z primary register
;
;-------------------------------------------------------
; Timer Z output control register
;-------------------------------------------------------
tyzoc .equ 008ah
tzoc .equ 008ah
;
tzos .btequ 0,tzoc ; Timer Z one-shot start bit
tzocnt .btequ 2,tzoc ; Timer Z programmable waveform generation output switching bit
;
;-------------------------------------------------------
; Timer X mode register
;-------------------------------------------------------
txmr .equ 008bh
;
txmod0 .btequ 0,txmr ; Operation mode select bit0
txmod1 .btequ 1,txmr ; Operation mode select bit1
r0edg .btequ 2,txmr ; INT1/CNTR0 polarity switching bit
txs .btequ 3,txmr ; Timer X count start flag
txocnt .btequ 4,txmr ; P30/CNTR0 select bit
txmod2 .btequ 5,txmr ; Operation mode select bit2
txedg .btequ 6,txmr ; Active edge reception flag
txund .btequ 7,txmr ; Timer X under flow flag
;
;-------------------------------------------------------
; Timer X registers
;-------------------------------------------------------
prex .equ 008ch ; Prescaler X register
;
tx .equ 008dh ; Timer X register
;
;-------------------------------------------------------
; Timer count source setting register
;-------------------------------------------------------
tcss .equ 008eh
;
txck0 .btequ 0,tcss ; Timer X count source select bit
txck1 .btequ 1,tcss ;
tzck0 .btequ 4,tcss ; Timer Z count source select bit
tzck1 .btequ 5,tcss ;
;
;-------------------------------------------------------
; Timer C registers
;-------------------------------------------------------
tc .equ 0090h ; Timer C
tcl .equ tc ; Low
tch .equ tc+1 ; High
;
;-------------------------------------------------------
; External input enable register
;-------------------------------------------------------
inten .equ 0096h
;
int0en .btequ 0,inten ; INT0 input enable bit
int0pl .btequ 1,inten ; INT0 input polarity select bit
;
;-------------------------------------------------------
; Key input enable register
;-------------------------------------------------------
kien .equ 0098h
ki0en .btequ 0,kien ; KI0 input enable bit
ki0pl .btequ 1,kien ; KI0 input polarity select bit
ki1en .btequ 2,kien ; KI1 input enable bit
ki1pl .btequ 3,kien ; KI1 input polarity select bit
ki2en .btequ 4,kien ; KI2 input enable bit
ki2pl .btequ 5,kien ; KI2 input polarity select bit
ki3en .btequ 6,kien ; KI3 input enable bit
ki3pl .btequ 7,kien ; KI3 input polarity select bit
;
;-------------------------------------------------------
; Timer C control register0
;-------------------------------------------------------
tcc0 .equ 009ah
tcc00 .btequ 0,tcc0 ; Timer C control bit
tcc01 .btequ 1,tcc0 ; Timer C count source select bit
tcc02 .btequ 2,tcc0 ;
tcc03 .btequ 3,tcc0 ; INT3 interrupt and capture polarity select bit
tcc04 .btequ 4,tcc0 ;
tcc06 .btequ 6,tcc0 ; INT3 interrupt request generation timing select bit
tcc07 .btequ 7,tcc0 ; INT3 interrupt/capture input switching bit
;
;-------------------------------------------------------
; Timer C control register1
;-------------------------------------------------------
tcc1 .equ 009bh
tcc10 .btequ 0,tcc1 ; INT3 input filter select bit
tcc11 .btequ 1,tcc1 ;
tcc12 .btequ 2,tcc1 ; Timer C counter reload select bit
tcc13 .btequ 3,tcc1 ; Compare0/capture select bit
tcc14 .btequ 4,tcc1 ; Compare0 output mode select bit
tcc15 .btequ 5,tcc1 ;
tcc16 .btequ 6,tcc1 ; Compare1 output mode select bit
tcc17 .btequ 7,tcc1 ;
;
;-------------------------------------------------------
; Capture and compare0 register
;-------------------------------------------------------
tm0 .equ 009ch ; Capture and compare0 register
tm0l .equ tm0 ; Low
tm0h .equ tm0+1 ; High
;
;-------------------------------------------------------
; Compare1 register
;-------------------------------------------------------
tm1 .equ 009eh ; Compare1 register
tm1l .equ tm1 ; Low
tm1h .equ tm1+1 ; High
;
;-------------------------------------------------------
; UART0
;-------------------------------------------------------
u0mr .equ 00a0h ; UART0 transmit/receive mode register
smd0_u0mr .btequ 0,u0mr ; Serial I/O mode select bit
smd1_u0mr .btequ 1,u0mr ;
smd2_u0mr .btequ 2,u0mr ;
ckdir_u0mr .btequ 3,u0mr ; Internal/external clock select bit
stps_u0mr .btequ 4,u0mr ; Stop bit length select bit
pry_u0mr .btequ 5,u0mr ; Odd/even parity select bit
prye_u0mr .btequ 6,u0mr ; Parity enable bit
;
u0brg .equ 00a1h ; UART0 bit rate generator ; Use "MOV" instruction when writing to this register.
;
u0tb .equ 00a2h ; UART0 transmit buffer register ; Use "MOV" instruction when writing to this register.
u0tbl .equ u0tb ; Low
u0tbh .equ u0tb+1 ; High
;
u0c0 .equ 00a4h ; UART0 transmit/receive control register0
clk0_u0c0 .btequ 0,u0c0 ; BRG count source select bit
clk1_u0c0 .btequ 1,u0c0 ;
txept_u0c0 .btequ 3,u0c0 ; Transmit register empty flag
nch_u0c0 .btequ 5,u0c0 ; Data output select bit
ckpol_u0c0 .btequ 6,u0c0 ; CLK polarity select bit
uform_u0c0 .btequ 7,u0c0 ; Transfer format select bit
;
u0c1 .equ 00a5h ; UART0 transmit/receive control register1
te_u0c1 .btequ 0,u0c1 ; Transmit enable bit
ti_u0c1 .btequ 1,u0c1 ; Transmit buffer empty flag
re_u0c1 .btequ 2,u0c1 ; Receive enable bit
ri_u0c1 .btequ 3,u0c1 ; Receive complete flag
;
u0rb .equ 00a6h ; UART0 receive buffer register
u0rbl .equ u0rb ; Low
u0rbh .equ u0rb+1 ; High
oer_u0rb .btequ 4,u0rbh ; Overrun error flag
fer_u0rb .btequ 5,u0rbh ; Framing error flag
per_u0rb .btequ 6,u0rbh ; Parity error flag
sum_u0rb .btequ 7,u0rbh ; Error sum flag
;
;-------------------------------------------------------
; UART1
;-------------------------------------------------------
u1mr .equ 00a8h ; UART1 transmit/receive mode register
smd0_u1mr .btequ 0,u1mr ; Serial I/O mode select bit
smd1_u1mr .btequ 1,u1mr ;
smd2_u1mr .btequ 2,u1mr ;
ckdir_u1mr .btequ 3,u1mr ; Internal/external clock select bit
stps_u1mr .btequ 4,u1mr ; Stop bit length select bit
pry_u1mr .btequ 5,u1mr ; Odd/even parity select bit
prye_u1mr .btequ 6,u1mr ; Parity enable bit
;
u1brg .equ 00a9h ; UART1 bit rate generator ; Use "MOV" instruction when writing to this register.
;
u1tb .equ 00aah ; UART1 transmit buffer register ; Use "MOV" instruction when writing to this register.
u1tbl .equ u1tb ; Low
u1tbh .equ u1tb+1 ; High
;
u1c0 .equ 00ach ; UART1 transmit/receive control register0
clk0_u1c0 .btequ 0,u1c0 ; BRG count source select bit
clk1_u1c0 .btequ 1,u1c0 ;
txept_u1c0 .btequ 3,u1c0 ; Transmit register empty flag
nch_u1c0 .btequ 5,u1c0 ; Data output select bit
ckpol_u1c0 .btequ 6,u1c0 ; CLK polarity select bit
uform_u1c0 .btequ 7,u1c0 ; Transfer format select bit
;
u1c1 .equ 00adh ; UART1 transmit/receive control register1
te_u1c1 .btequ 0,u1c1 ; Transmit enable bit
ti_u1c1 .btequ 1,u1c1 ; Transmit buffer empty flag
re_u1c1 .btequ 2,u1c1 ; Receive enable bit
ri_u1c1 .btequ 3,u1c1 ; Receive complete flag
;
u1rb .equ 00aeh ; UART1 receive buffer register
u1rbl .equ u1rb ; Low
u1rbh .equ u1rb+1 ; High
oer_u1rb .btequ 4,u1rbh ; Overrun error flag
fer_u1rb .btequ 5,u1rbh ; Framing error flag
per_u1rb .btequ 6,u1rbh ; Parity error flag
sum_u1rb .btequ 7,u1rbh ; Error sum flag
;
ucon .equ 00b0h ; UART transmit/receive control register2
u0irs .btequ 0,ucon ; UART0 transmit interrupt cause select bit
u1irs .btequ 1,ucon ; UART1 transmit interrupt cause select bit
u0rrm .btequ 2,ucon ; UART0 continuous receive mode enable bit
u1sel0 .btequ 4,ucon ; UART1 pin (P3_7/TXD1,P4_5/RXD1) select bit
u1sel1 .btequ 5,ucon ; UART1 pin (P3_7/TXD1,P4_5/RXD1) select bit
cntrsel .btequ 7,ucon ; Cntr0 signal pin select bit
;
;-------------------------------------------------------
; SS control register H
;-------------------------------------------------------
sscrh .equ 00b8h
;
cks0_sscrh .btequ 0,sscrh ; Transfer clock rate select bit
cks1_sscrh .btequ 1,sscrh ;
cks2_sscrh .btequ 2,sscrh ;
mss_sscrh .btequ 5,sscrh ; Master/Slave device select bit
rsstp_sscrh .btequ 6,sscrh ; Receive single stop bit
;
;-------------------------------------------------------
; SS control register L
;-------------------------------------------------------
sscrl .equ 00b9h
;
sres_sscrl .btequ 1,sscrl ; SSUA control part reset bit
solp_sscrl .btequ 4,sscrl ; SOL write protect bit
sol_sscrl .btequ 5,sscrl ; Serial data output value setting bit
;
;-------------------------------------------------------
; SS mode register
;-------------------------------------------------------
ssmr .equ 00bah
;
bc0_ssmr .btequ 0,ssmr ; Bit counter 2 to 0
bc1_ssmr .btequ 1,ssmr ;
bc2_ssmr .btequ 2,ssmr ;
cphs_ssmr .btequ 5,ssmr ; SSCK clock phase select bit
cpos_ssmr .btequ 6,ssmr ; SSCK clock polarity select bit
mls_ssmr .btequ 7,ssmr ; MSB first/ LSB first select bit
;
;-------------------------------------------------------
; SS enable register
;-------------------------------------------------------
sser .equ 00bbh
;
ceie_sser .btequ 0,sser ; Conflict error interrupt enable bit
re_sser .btequ 3,sser ; Receive enable bit
te_sser .btequ 4,sser ; Transmit enable bit
rie_sser .btequ 5,sser ; Receive interrupt enable bit
teie_sser .btequ 6,sser ; Transmit end interrupt enable bit
tie_sser .btequ 7,sser ; Transmit interrupt enable bit
;
;-------------------------------------------------------
; SS status register
;-------------------------------------------------------
sssr .equ 00bch
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