sfr_r81b.inc

瑞萨单片机串口通讯的完整例程

;------------------------------------------------------------------------
;                                                                       |
;   FILE        :sfr_r81B.inc                                           |
;   DATE        :Tue, Feb 17, 2009                                      |
;   DESCRIPTION :define the sfr register. (for Assembler language)      |
;   CPU GROUP   :1B                                                     |
;                                                                       |
;   This file is generated by Renesas Project Generator (Ver.4.12).     |
;                                                                       |
;------------------------------------------------------------------------

;************************************************************************************
;*																					*
;*  file name   : SFR_R81B.inc														*
;*  Contents    : definition of R8C/1A & R8C/1B Group SFR							*
;*																					*
;*  Copyright, 2005 RENESAS TECHNOLOGY CORPORATION									*
;*                  AND RENESAS SOLUTIONS CORPORATION								*
;*																					*
;*  Version     : 1.10 (06-04-03)                                                   *
;*                     add : ssuaic and iic2aic										*
;*                1.00 (05-06-10)													*
;*																					*
;*																					*
;************************************************************************************
;
;-------------------------------------------------------
;   Processor mode register0
;-------------------------------------------------------
pm0				.equ		0004h
;
pm03			.btequ		3,pm0		; Software reset bit
;
;-------------------------------------------------------
;   Processor mode register1
;-------------------------------------------------------
pm1				.equ		0005h
;
pm12			.btequ		2,pm1		; WDT interrupt/reset select bit
;
;-------------------------------------------------------
;   System clock control register0
;-------------------------------------------------------
cm0				.equ		0006h
;
cm02			.btequ		2,cm0		; WAIT peripheral function clock stop bit
cm05			.btequ		5,cm0		; Main clock (Xin-Xout) stop bit
cm06			.btequ		6,cm0		; Main clock division select bit0
;
;-------------------------------------------------------
;   System clock control register1
;-------------------------------------------------------
cm1				.equ		0007h
;	
cm10			.btequ		0,cm1		; All clock stop control bit
cm13			.btequ		3,cm1		; Port Xin-Xout switch bit
cm14			.btequ		4,cm1		; Low-speed on-chip oscillator stop bit
cm15			.btequ		5,cm1		; Xin-Xout drive capability select bit
cm16			.btequ		6,cm1		; Main clock division select bit1
cm17			.btequ		7,cm1		;
;
;-------------------------------------------------------
;   Address match interrupt enable register
;-------------------------------------------------------
aier			.equ		0009h
;
aier0			.btequ		0,aier		; Address match interrupt 0 enable bit
aier1			.btequ		1,aier		; Address match interrupt 1 enable bit
;
;-------------------------------------------------------
;   Protect register
;-------------------------------------------------------
prcr			.equ		000ah
;
prc0			.btequ		0,prcr		; Protect bit0
prc1			.btequ		1,prcr		; Protect bit1
prc3			.btequ		3,prcr		; Protect bit3;
;
;-------------------------------------------------------
;   Oscillation stop detection register
;-------------------------------------------------------
ocd				.equ		000ch
;
ocd0			.btequ		0,ocd		; Oscillation stop detection enable bit
ocd1			.btequ		1,ocd		;
ocd2			.btequ		2,ocd		; System clock select bit
ocd3			.btequ		3,ocd		; Clock monitor bit
;
;-------------------------------------------------------
;   Watchdog timer
;-------------------------------------------------------
wdtr			.equ		000dh		; Watchdog timer reset register
;
wdts			.equ		000eh		; Watchdog timer start register
;
wdc				.equ		000fh		; Watchdog timer control register
;
wdc7			.btequ		7,wdc		; Prescaler select bit
;
;-------------------------------------------------------
;   Address match interrupt register0
;-------------------------------------------------------
rmad0			.equ		0010h
rmad0l			.equ		rmad0		; Address match interrupt register0 Low
rmad0m			.equ		rmad0+1		; Address match interrupt register0 Middle
rmad0h			.equ		rmad0+2		; Address match interrupt register0 High
;
;-------------------------------------------------------
;   Address match interrupt register1
;-------------------------------------------------------
rmad1			.equ		0014h
rmad1l			.equ		rmad1		; Address match interrupt register1 Low
rmad1m			.equ		rmad1+1		; Address match interrupt register1 Middle
rmad1h			.equ		rmad1+2		; Address match interrupt register1 High
;
;-------------------------------------------------------
;   Count source protect mode register
;-------------------------------------------------------
cspr			.equ		001ch
;
cspro			.btequ		7,cspr		; WDT count source protect mode select bit
;
;-------------------------------------------------------
;   INT0 input filter select register
;-------------------------------------------------------
int0f			.equ		001eh
;
int0f0			.btequ		0,int0f		; INT0 input filter select bit
int0f1			.btequ		1,int0f		;
;
;;-------------------------------------------------------
;   High speed on-chip oscillator A control register0
;-------------------------------------------------------
hra0			.equ		0020h
;
hra00			.btequ		0,hra0		; High speed on-chip oscillator A enable bit
hra01			.btequ		1,hra0		; High speed on-chip oscillator A select bit
;
;-------------------------------------------------------
;   High speed on-chip oscillator A control register1
;-------------------------------------------------------
hra1			.equ		0021h
;
;-------------------------------------------------------
;   High speed on-chip oscillator A control register2
;-------------------------------------------------------
hra2			.equ		0022h
;
hra20			.btequ		0,hra2		; High speed on-chip oscillator moed select bit
hra21			.btequ		1,hra2		; High speed on-chip oscillator moed select bit
;
;-------------------------------------------------------
;   Voltage detection A register1
;-------------------------------------------------------
vca1			.equ		0031h
;
vca13			.btequ		3,vca1		; Voltage detection 2 signal monitor flag
;
;-------------------------------------------------------
;   Voltage detection A register2
;-------------------------------------------------------
vca2			.equ		0032h
;
vca26			.btequ		6,vca2		; Voltage enable bit
vca27			.btequ		7,vca2		; Voltage enable bit
;
;-------------------------------------------------------
;   Voltage monitor 1 circuit control register
;-------------------------------------------------------
vw1c			.equ		0036h
;
vw1c0			.btequ		0,vw1c		; Voltage monitor 1 reset enable bit
vw1c1			.btequ		1,vw1c		; Voltage Monitor 1 digital filter disable mode select bit
vw1c2			.btequ		2,vw1c		; Voltage change detection flag
vw1c3			.btequ		3,vw1c		; Voltage detection 1 signal monitor flag
vw1f0			.btequ		4,vw1c		; Sampling clock select bit
vw1f1			.btequ		5,vw1c		; Sampling clock select bit
vw1c6			.btequ		6,vw1c		; Voltage monitor 1 circuit mode select bit
vw1c7			.btequ		7,vw1c		; Voltage monitor 1 reset generating condition select bit
;
;-------------------------------------------------------
;   Voltage monitor 2 circuit control register
;-------------------------------------------------------
vw2c			.equ		0037h

vw2c0			.btequ		0,vw2c		; Voltage monitor 2 interrupt / reset enable bit
vw2c1			.btequ		1,vw2c		; Voltage monitor 2 digital filter disabled mode select bit
vw2c2			.btequ		2,vw2c		; Voltage change detection flag
vw2c3			.btequ		3,vw2c		; WDT Detection Flag
vw2f0			.btequ		4,vw2c		; Sampling clock select bit
vw2f1			.btequ		5,vw2c		; Sampling clock select bit
vw2c6			.btequ		6,vw2c		; Voltage monitor 2 circuit mode select bit
vw2c7			.btequ		7,vw2c		; Voltage monitor 2 interrupt / reset generating condition select bit
;                                     
;-------------------------------------------------------
;   Interrupt control registers
;-------------------------------------------------------
kupic			.equ		004dh		; Key input interrupt control register
ilvl0_kupic		.btequ		0,kupic		; Interrupt priority level select bit
ilvl1_kupic		.btequ		1,kupic		;
ilvl2_kupic		.btequ		2,kupic		;
ir_kupic		.btequ		3,kupic		; Interrupt request bit
;
adic			.equ		004eh		; Comparator conversion interrupt control register
ilvl0_adic		.btequ		0,adic		; Interrupt priority level select bit
ilvl1_adic		.btequ		1,adic		;
ilvl2_adic		.btequ		2,adic		;
ir_adic			.btequ		3,adic		; Interrupt request bit
;
ssuaic			.equ		004fh		; SSU interrupt control register
ilvl0_ssuaic	.btequ		0,ssuaic	; Interrupt priority level select bit
ilvl1_ssuaic	.btequ		1,ssuaic	;
ilvl2_ssuaic	.btequ		2,ssuaic	;
ir_ssuaic		.btequ		3,ssuaic	; Interrupt request bit
;
iic2aic			.equ		004fh		; IIC interrupt control register
ilvl0_iic2aic	.btequ		0,iic2aic	; Interrupt priority level select bit
ilvl1_iic2aic	.btequ		1,iic2aic	;
ilvl2_iic2aic	.btequ		2,iic2aic	;
ir_iic2aic		.btequ		3,iic2aic	; Interrupt request bit
;
cmp1ic			.equ		0050h		; Compare 1 interrupt control register
ilvl0_cmp1ic	.btequ		0,cmp1ic	; Interrupt priority level select bit
ilvl1_cmp1ic	.btequ		1,cmp1ic	;
ilvl2_cmp1ic	.btequ		2,cmp1ic	;
ir_cmp1ic		.btequ		3,cmp1ic	; Interrupt request bit
;
s0tic			.equ		0051h		; UART0 transmit interrupt control register
ilvl0_s0tic		.btequ		0,s0tic		; Interrupt priority level select bit
ilvl1_s0tic		.btequ		1,s0tic		;
ilvl2_s0tic		.btequ		2,s0tic		;
ir_s0tic		.btequ		3,s0tic		; Interrupt request bit
;
s0ric			.equ		0052h		; UART0 receive interrupt control register
ilvl0_s0ric		.btequ		0,s0ric		; Interrupt priority level select bit
ilvl1_s0ric		.btequ		1,s0ric		;
ilvl2_s0ric		.btequ		2,s0ric		;
ir_s0ric		.btequ		3,s0ric		; Interrupt request bit
;
s1tic			.equ		0053h		; UART1 transmit interrupt control register
ilvl0_s1tic		.btequ		0,s1tic		; Interrupt priority level select bit
ilvl1_s1tic		.btequ		1,s1tic		;
ilvl2_s1tic		.btequ		2,s1tic		;
ir_s1tic		.btequ		3,s1tic		; Interrupt request bit
;
s1ric			.equ		0054h		; UART1 receive interrupt control register
ilvl0_s1ric		.btequ		0,s1ric		; Interrupt priority level select bit
ilvl1_s1ric		.btequ		1,s1ric		;
ilvl2_s1ric		.btequ		2,s1ric		;
ir_s1ric		.btequ		3,s1ric		; Interrupt request bit
;
txic			.equ		0056h		; Timer X interrupt control register
ilvl0_txic		.btequ		0,txic		; Interrupt priority level select bit
ilvl1_txic		.btequ		1,txic		;
ilvl2_txic		.btequ		2,txic		;
ir_txic			.btequ		3,txic		; Interrupt request bit
;
tzic			.equ		0058h		; Timer Z interrupt control register
ilvl0_tzic		.btequ		0,tzic		; Interrupt priority level select bit
ilvl1_tzic		.btequ		1,tzic		;
ilvl2_tzic		.btequ		2,tzic		;
ir_tzic			.btequ		3,tzic		; Interrupt request bit
;
int1ic			.equ		0059h		; INT1 interrupt control register
ilvl0_int1ic	.btequ		0,int1ic	; Interrupt priority level select bit
ilvl1_int1ic	.btequ		1,int1ic	;
ilvl2_int1ic	.btequ		2,int1ic	;
ir_int1ic		.btequ		3,int1ic	; Interrupt request bit
;
int3ic			.equ		005ah		; INT3 interrupt control register
ilvl0_int3ic	.btequ		0,int3ic	; Interrupt priority level select bit
ilvl1_int3ic	.btequ		1,int3ic	;
ilvl2_int3ic	.btequ		2,int3ic	;
ir_int3ic		.btequ		3,int3ic	; Interrupt request bit
;
tcic			.equ		005bh		; Timer C interrupt control register
ilvl0_tcic		.btequ		0,tcic		; Interrupt priority level select bit
ilvl1_tcic		.btequ		1,tcic		;
ilvl2_tcic		.btequ		2,tcic		;
ir_tcic			.btequ		3,tcic		; Interrupt request bit
;
cmp0ic			.equ		005ch		; Compare 0 interrupt control register
ilvl0_cmp0ic	.btequ		0,cmp0ic	; Interrupt priority level select bit