i2c-algo-s3c2410.c

s3c2410 arm-linux-2.4.18 i2c master driver

	// setup transfer.  if NOSTART flag set, then transfer is already in
	// progress so skip init
	if (!(pmsg->flags & I2C_M_NOSTART)) {
	   // load slave address
	   DEB2(printk(KERN_DEBUG "s3c2410_sendbytes: Loading slave address\n"));
	   addr = iic_addr(adap, pmsg);
	   s3c2410_outb(adap, S3C2410_IICDS, addr);
	   udelay(5);   /* IICSDA setup delay */

	   // set transmit mode
	   DEB2(printk(KERN_DEBUG "s3c2410_sendbytes: Set transmit mode\n"));
	   ret = S3C2410_IICSTAT_MTX_ENABLE;
	   s3c2410_outb(adap, S3C2410_IICSTAT, ret);

	   ret = s3c2410_inb(adap, S3C2410_IICSTAT);
	   ret = s3c2410_inb(adap, S3C2410_IICSTAT);

	   // wait for transmit of slave addr to complete
	   if ((rval = s3c2410_wait(i2c_adap, 1)) < 0)
	      return rval;
	}

	// loop through and send data bytes
	for (i = 0; i < count; i++) {
	   // write next byte to the shift register
	   s3c2410_outb(adap, S3C2410_IICDS, buf[i]);
	   udelay(5);   /* IICSDA setup delay */

	   // clear the pending bit
	   ret = s3c2410_inb(adap, S3C2410_IICCON);
	   s3c2410_outb(adap, S3C2410_IICCON, ret & ~S3C2410_IICCON_INT_PEND);

	   // Wait for transmission to complete.
	   if ((rval = s3c2410_wait(i2c_adap, 1)) < 0)
	      return (i);
	}

	// if this is a single write, stop now that we're done
	if (xfer_flag == IIC_SINGLE_XFER) {
	   // generate a STOP condition
	   ret = s3c2410_inb(adap, S3C2410_IICSTAT);
	   s3c2410_outb(adap, S3C2410_IICSTAT, ret & ~S3C2410_IICSTAT_BUSY);

	   // clear the pending bit
	   ret = s3c2410_inb(adap, S3C2410_IICCON);
	   s3c2410_outb(adap, S3C2410_IICCON, ret & ~S3C2410_IICCON_INT_PEND);
	}

	return (i);
}


//
// Description: This function is called by the upper layers to do the
// grunt work for a master receive transaction
//
static int s3c2410_readbytes(struct i2c_adapter *i2c_adap,
                             struct i2c_msg *pmsg, int xfer_flag)
{
	struct i2c_algo_s3c2410_data *adap = i2c_adap->algo_data;
	int i, count, ret, busystat;
	char *buf;
	u8 addr;
	int rval;

	buf = pmsg->buf;
	count = pmsg->len;
   
	if( count == 0 ) return 0;

	// check for start/busy condition in progress
	busystat = s3c2410_inb(adap, S3C2410_IICSTAT);

	DEB(printk(KERN_DEBUG "I2C READ s3c2410_readbytes: len=%d   addr=0x%04x   flags=0x%04x\n", pmsg->len, pmsg->addr, pmsg->flags));

	// setup transfer.  if NOSTART flag set, then transfer is already in
	// progress so skip init
	if (!(pmsg->flags & I2C_M_NOSTART)) {
	   // load slave address (unless NOSTART flag is set)
	   DEB2(printk(KERN_DEBUG "s3c2410_readbytes: Loading slave address\n"));
	   addr = iic_addr(adap, pmsg);
	   s3c2410_outb(adap, S3C2410_IICDS, addr);
	   udelay(5);   /* IICSDA setup delay */

	   // set receive mode
	   DEB2(printk(KERN_DEBUG "s3c2410_readbytes: Set receive mode\n"));
	   ret = S3C2410_IICSTAT_MRX_ENABLE;
	   s3c2410_outb(adap, S3C2410_IICSTAT, ret);

	   // wait for transmit of slave addr to complete
	   if ((rval = s3c2410_wait(i2c_adap, 1)) < 0)
	      return rval;
	}

	// loop through and read data bytes
	// if a start condition was already in progress, do a dummy read
	for (i = (busystat & S3C2410_IICSTAT_BUSY)?0:1; i < (count+1); i++) {

	   // if this is the last byte, disable ACK generation
           if (i == count) {
               ret = s3c2410_inb(adap, S3C2410_IICCON);
	       s3c2410_outb(adap, S3C2410_IICCON, ret & ~S3C2410_IICCON_ACK_EN);
           }

	   // clear the pending bit
	   ret = s3c2410_inb(adap, S3C2410_IICCON);
	   s3c2410_outb(adap, S3C2410_IICCON, ret & ~S3C2410_IICCON_INT_PEND);

	   // Wait for transmission to complete.
	   if ((rval = s3c2410_wait(i2c_adap, 0)) < 0) {
	      return ((i <= 0) ? rval : i-1);
	   }

	   // read next byte from the shift register
	   if (i == 0)
	       s3c2410_inb(adap, S3C2410_IICDS);   // dummy read
	   else
	       buf[i-1] = s3c2410_inb(adap, S3C2410_IICDS);
	}

	// if this is a single read, stop now that we're done
	if (xfer_flag == IIC_SINGLE_XFER) {
	   // generate a STOP condition
	   ret = s3c2410_inb(adap, S3C2410_IICSTAT);
	   s3c2410_outb(adap, S3C2410_IICSTAT, ret & ~S3C2410_IICSTAT_BUSY);

	   // clear the pending bit and re-enable ACK generation
	   ret = s3c2410_inb(adap, S3C2410_IICCON);
	   ret = (ret & ~S3C2410_IICCON_INT_PEND) | S3C2410_IICCON_ACK_EN;
	   s3c2410_outb(adap, S3C2410_IICCON, ret);
	}

	return count;
}



//
// Description:  This function implements combined transactions.  Combined
// transactions consist of combinations of reading and writing blocks of data.
// Each transfer (i.e. a read or a write) is separated by a repeated start
// condition.
//
static int s3c2410_combined_transaction(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num) 
{
   int i;
   struct i2c_msg *pmsg;
   int ret;

   DEB2(printk(KERN_DEBUG "Beginning combined transaction\n"));

   for(i=0; i<(num-1); i++) {
      pmsg = &msgs[i];
      if(pmsg->flags & I2C_M_RD) {
         DEB2(printk(KERN_DEBUG "  This one is a read\n"));
         ret = s3c2410_readbytes(i2c_adap, pmsg, IIC_COMBINED_XFER);
      }
      else if(!(pmsg->flags & I2C_M_RD)) {
         DEB2(printk(KERN_DEBUG "This one is a write\n"));
         ret = s3c2410_sendbytes(i2c_adap, pmsg, IIC_COMBINED_XFER);
      }
   }
   //
   // Last read or write segment needs to be terminated with a stop
   //
   pmsg = &msgs[i];

   if(pmsg->flags & I2C_M_RD) {
      DEB2(printk(KERN_DEBUG "Doing the last read\n"));
      ret = s3c2410_readbytes(i2c_adap, pmsg, IIC_SINGLE_XFER);
   }
   else if(!(pmsg->flags & I2C_M_RD)) {
      DEB2(printk(KERN_DEBUG "Doing the last write\n"));
      ret = s3c2410_sendbytes(i2c_adap, pmsg, IIC_SINGLE_XFER);
   }

   return ret;
}


//
// Description: Prepares the controller for a transaction (clearing status
// registers, data buffers, etc), and then calls either s3c2410_readbytes or
// s3c2410_sendbytes to do the actual transaction.
//
static int s3c2410_xfer(struct i2c_adapter *i2c_adap,
		    struct i2c_msg msgs[], 
		    int num)
{
	struct i2c_algo_s3c2410_data *adap = i2c_adap->algo_data;
	struct i2c_msg *pmsg;
	int i = 0;
	int ret = 0;
    
	pmsg = &msgs[i];

	//
	// get the I2C controller/bus back to a sane state
	//

	if (s3c2410_reset(adap) < 0)
	  return -EIO;

	//
	// Combined transaction (read and write)
	//
	if(num > 1) {
           DEB2(printk(KERN_DEBUG "s3c2410_xfer: Call combined transaction\n"));
           ret = s3c2410_combined_transaction(i2c_adap, msgs, num);
        }
	//
	// Read only
	//
	else if((num == 1) && (pmsg->flags & I2C_M_RD)) {
	   //
	   // Tell device to begin reading data from the  master data 
	   //
	   DEB2(printk(KERN_DEBUG "s3c2410_xfer: Call adapter's read\n"));
	   ret = s3c2410_readbytes(i2c_adap, pmsg, IIC_SINGLE_XFER);
	} 
        //
	// Write only
	//
	else if((num == 1 ) && (!(pmsg->flags & I2C_M_RD))) {
	   //
	   // Write data to master data buffers and tell our device
	   // to begin transmitting
	   //
	   DEB2(printk(KERN_DEBUG "s3c2410_xfer: Call adapter's write\n"));
	   ret = s3c2410_sendbytes(i2c_adap, pmsg, IIC_SINGLE_XFER);
	}	

	return ret;   
}


//
// Description: Implements device specific ioctls.  Higher level ioctls can
// be found in i2c-core.c and are typical of any i2c controller (specifying
// slave address, timeouts, etc).  These ioctls take advantage of any hardware
// features built into the controller for which this algorithm-adapter set
// was written.
//
static int algo_control(struct i2c_adapter *adapter, 
	unsigned int cmd, unsigned long arg)
{
	if (cmd == I2C_S3C2410_SET_SPEED) {
		if ((arg % 100) > 15  ||  (arg / 100) > 1)
			return -EINVAL;
		i2c_clkdiv = arg;
		return 0;
	} else if (cmd == I2C_S3C2410_GET_SPEED) {
		/* return speed in kHz */
		unsigned long speed = s3c2410_clkspeed();
		if (copy_to_user( (unsigned long*)arg, &speed, sizeof(speed)) ) 
			return -EFAULT;
		return 0;
	}

	return -EINVAL;
}




static u32 s3c2410_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 
}


/* ----- exported algorithm data: -------------------------------------	*/

static struct i2c_algorithm s3c2410_algo = {
	"Samsung S3C2410X algorithm",
	I2C_ALGO_S3C2410,
	s3c2410_xfer,
	NULL,
	NULL,				/* slave_xmit		*/
	NULL,				/* slave_recv		*/
	algo_control,			/* ioctl		*/
	s3c2410_func,			/* functionality	*/
};


/* 
 * registering functions to load algorithms at runtime 
 */


//
// Description: Register bus structure
//
int i2c_s3c2410_add_bus(struct i2c_adapter *adap)
{
//	int i, status;
	struct i2c_algo_s3c2410_data *s3c2410_adap = adap->algo_data;

	DEB2(printk(KERN_DEBUG "i2c-algo-s3c2410.o: hw routines for %s registered.\n",
	            adap->name));

	/* register new adapter to i2c module... */

	adap->id |= s3c2410_algo.id;
	adap->algo = &s3c2410_algo;

	adap->timeout = 100;		/* default values, should	*/
	adap->retries = 3;		/* be replaced by defines	*/

#ifdef MODULE
	MOD_INC_USE_COUNT;
#endif

	s3c2410_init(s3c2410_adap);
	i2c_add_adapter(adap);
        printk("s3c2410_init: Initialized IIC on S3C2410X, %dkHz clock\n",
               s3c2410_clkspeed());

	return 0;
}


//
// Done
//
int i2c_s3c2410_del_bus(struct i2c_adapter *adap)
{
	int res;
	if ((res = i2c_del_adapter(adap)) < 0)
		return res;
	DEB2(printk(KERN_DEBUG "i2c-algo-s3c2410.o: adapter unregistered: %s\n",adap->name));

#ifdef MODULE
	MOD_DEC_USE_COUNT;
#endif
	return 0;
}


//
// Done
//
int __init i2c_algo_s3c2410_init (void)
{
	printk(KERN_INFO "Samsung S3C2410X (i2c) algorithm module version %s (%s)\n", I2C_VERSION, I2C_DATE);
	return 0;
}


void i2c_algo_s3c2410_exit(void)
{
	return;
}


EXPORT_SYMBOL(i2c_s3c2410_add_bus);
EXPORT_SYMBOL(i2c_s3c2410_del_bus);
EXPORT_SYMBOL(s3c2410_i2c_debug);


#ifndef MODULE

static int __init i2cdebug_setup(char *str)
{
	s3c2410_i2c_debug = simple_strtoul(str,NULL,10);
	return 1;
}

static int __init i2cclk_setup(char *str)
{
	i2c_clkdiv = simple_strtoul(str,NULL,10);
	return 1;
}


__setup("i2c_debug=", i2cdebug_setup);
__setup("i2c_clk=", i2cclk_setup);

#endif /* MODULE */


//
// The MODULE_* macros resolve to nothing if MODULES is not defined
// when this file is compiled.
//
MODULE_AUTHOR("Steve Hein   SGI Inc. <[e-mail]>");
MODULE_DESCRIPTION("Samsung S3C2410X/SMDK2410 algorithm");

MODULE_PARM(s3c2410_i2c_debug,"i");

MODULE_PARM_DESC(s3c2410_i2c_debug,
        "debug level - 0 off; 1 normal; 2,3 more verbose; 9 iic-protocol");


//
// This function resolves to init_module (the function invoked when a module
// is loaded via insmod) when this file is compiled with MODULES defined.
// Otherwise (i.e. if you want this driver statically linked to the kernel),
// a pointer to this function is stored in a table and called
// during the intialization of the kernel (in do_basic_setup in /init/main.c) 
//
// All this functionality is complements of the macros defined in linux/init.h
module_init(i2c_algo_s3c2410_init);


//
// If MODULES is defined when this file is compiled, then this function will
// resolved to cleanup_module.
//
module_exit(i2c_algo_s3c2410_exit);