usb 1_1 for usb otg implementation - patent 7193442.htm

usb softconnection configration

default slave. </P>
<P>Consider the example where A-device <B>326 </B>is default host device and 
conducts data transmission according to USB timing requirements. A-device <B>326 
</B>via gated power/reset block <B>305 </B>starts a session by performing a bus 
reset and powers up Vbus via USB power management block <B>306 </B>. Normal bus 
activity then can take place including transfer of control and data information 
from the A-device to the B-device via the differential data bus, which includes 
twisted pair lines D+ <B>316 </B>and D− <B>317 </B>. Normal bus activity 
concludes when the data transfer is complete. This could include hundreds of 
frames of data. At this point A-device <B>326 </B>can enter a shut-down or sleep 
mode and cut off power to the Vbus line via USB power management block <B>306 
</B>. Once normal bus activity ceases, a time window of 100 milliseconds (100 
frames) is open for the B-device to request the start of a new session under 
session request protocol. </P>
<P>In session request protocol the B-device <B>327 </B>requests a new session 
from A-device in sleep mode by executing the following steps: </P>
<P>1. Vbus/Dataline detect: Detect Vbus less than 0.8 volts and D+ and D−low for 
2 mS. This is performed by Vbus detect block <B>310 </B>and D+/D− detect block 
<B>313 </B>. </P>
<P>2. Dataline pulsing: B-device <B>327 </B>must perform dataline pulsing by 
switching in pull-up resistors via block <B>312 </B>for a period of 5 to 10 mS. 
</P>
<P>3. Vbus pulsing: B-device <B>327 </B>must perform Vbus pulsing by switching 
in pull-up resistors via block <B>309 </B>until Vbus is greater than 2.1 volts. 
</P>
<P>4. B-device <B>327 </B>must allow A-device 5 seconds minimum to respond. 
After 5 seconds, B-device <B>327 </B>may repeat steps <B>1 </B>– <B>3 </B>. 
During the 5 seconds allotted, A-device <B>326 </B>must perform the following 
steps: </P>
<P>5. Detect dataline pulsing: performed by the USB 1.1 device microcontroller 
sensing inputs <B>316 </B>and <B>317 </B>from D+/D− lines respectively. </P>
<P>6. Detect Vbus pulsing: performed by the block <B>301 </B>of modified USB 1.1 
device. This is illustrated in FIG. 5. Circuit block <B>301 </B>is dual function 
performing both Vbus pulsing detect in the configuration of FIG. 3 and 
performing Vbus off detection in the reversed connection of FIG. 4. Circuit 
block <B>301 </B>is a dual function performing both Vbus pulsing detect in the 
configuration of FIG. 3 and performing Vbus off detection in the reversed 
connection of FIG. 4. OTG Vbus detect line <B>323 </B>is fed to microcontroller 
<B>300 </B>which acknowledges a valid session request from B-device <B>326 
</B>by performing a reset and via block <B>305 </B>then powers up Vbus via block 
<B>306 </B>. </P>
<P>The B-device Vbus pulsing circuitry must limit the maximum current drawn by 
the B-Device to 8 mA. This restriction is met by having the Vbus pull-up block 
<B>309 </B>drive Vbus with a voltage source greater than 3.0 volts and with an 
output impedance greater than 280 ohms. </P>
<P>In host negotiation protocol the B-device <B>327 </B>requests a new session 
from the A-device <B>326 </B>in sleep mode. Host negotiation protocol (HNP) is 
used to transfer control of a connection from the default host (A-device) to the 
default Peripheral (B-device). This is accomplished by A-device <B>326 
</B>preparing or conditioning the B-device <B>327 </B>to be able to take control 
of the bus and then A-device <B>326 </B>presenting an opportunity for the 
B-device <B>327 </B>to take control. </P>
<P>A-device <B>326 </B>will complete the handoff by turning on the pull-up 
resistor on D+ line <B>316 </B>. This switched resistor is internal to the USB 
1.1 device microcontroller <B>300 </B>. </P>
<P>When the B-device <B>327 </B>has finished using the bus, it returns host 
control to A-device <B>326 </B>by stopping all bus activity and turning on its 
D+ pull-up resistor. A-device <B>326 </B>detects this lack of activity and turns 
off its pull-up resistor. When the A-device <B>326 </B>detects the connection 
from the B-device <B>327 </B>, it resumes bus operation as host. </P>
<P>The sequence of events in host negotiation protocol (HNP) is as follows: </P>
<P>1. At the conclusion of a session periodically the A-device <B>326 </B>sends 
a set feature enable (SFE) command over D+/D− lines <B>316 </B>/ <B>317 
</B>preparing the B-device for possible HNP. After sending this command, 
A-device <B>326 </B>suspends data transmission activity to signal the B-device 
that it may now take control of the bus. </P>
<P>2. B-device <B>327 </B>detects in block <B>310 </B>that bus is idle for more 
than 3 mS and begins (HNP) by turning off pull-up on D+. This pull-up is 
contained within block <B>312 </B>. This allows the bus to discharge to the 
session end zero SEO state. </P>
<P>3. The A-device <B>326 </B>detects the SEO on the bus and recognizes this as 
a request from the B-device <B>327 </B>to become host. A-device <B>327 
</B>responds by turning on its D+ pull-up resistor within 3 mS of first 
detecting the SEO on the bus. This pull-up is contained within microcontroller 
<B>300 </B>of the A-device <B>326 </B>. </P>
<P>4. After waiting long enough to insure that the D+ line cannot be high due to 
the residual effect of B-device <B>327 </B>pull-up, B-device <B>327 </B>detects 
in block <B>313 </B>that the D+ line is high and D− is low. This indicates that 
the A-device <B>326 </B>has recognized the HNP request from B-device <B>327 
</B>. B-device <B>327 </B>then becomes host and asserts bus reset to start using 
the bus. B-device <B>327 </B>must assert the bus reset (SEO) within 1.0 mS of 
the time that A-device <B>326 </B>turns on its pull-up in step <B>3 </B>. </P>
<P>5. When B-device <B>327 </B>completes using the bus, it stops all bus 
activity. </P>
<P>6. A-device <B>326 </B>detects the lack of bus activity for more than 3 mS 
via block <B>301 </B>and turns off its D+ pull-up. Alternatively, if the 
A-device <B>326 </B>has no further need to communicate with B-device <B>327 
</B>, the A-device <B>326 </B>may turn off Vbus and end the session. </P>
<P>7. B-device <B>327 </B>turns on its pull-up within block <B>312 
</B>signifying that it is relinquishing host status. </P>
<P>8. After waiting long enough to insure that the D+ line cannot be high due to 
the residual effect of the A-device pull-up, the A-device sees that the D+ line 
is high (and D−low) indicating that the B-device is signaling a connect and is 
ready to respond as a slave device peripheral. At this point, the A-device 
becomes host and asserts bus reset to start using the bus. </P>
<P>FIG. 4 illustrates the USB 1.1 to USB 2.0 OTG microcontroller <B>400 </B>and 
interface hardware functions <B>401 </B>through <B>406 </B>and their required 
interconnect to the USB 2.0 B-connector <B>421 </B>side of the interface. USB 
cabling consists of D+ and D− data lines, <B>416 </B>and <B>417 
</B>respectively, Vbus (Power supply) line <B>418 </B>, GND <B>419 </B>and USB 
ID detect line <B>420 </B>. An USB 2.0 OTG A-device comprising microcontroller 
<B>415 </B>and interface hardware functions <B>408 </B>through <B>413 </B>are 
connected to the USB cable through an A-connector <B>422 </B>. Hardware 
functions <B>401 </B>through <B>406 </B>upgrade the normal USB 1.1 capability to 
a modified USB 1.1 having USB 2.0 OTG compatibility. The A-device portion of 
FIG. 4 illustrates in symbolic form the hardware necessary to implement the USB 
2.0 OTG requirements and the SRP and HNP protocols described above. This 
includes functional blocks <B>408 </B>through <B>413 </B>and microcontroller 
<B>415 </B>. The detailed content of these functions of the USB 2.0 OTG B-device 
is not a part of the invention. The functions performed in FIG. 4 exactly mirror 
the functions described in FIG. 3. </P>
<P>FIG. 5 illustrates the schematic diagram of the OTG Vbus Pulsing Detect 
circuits <B>301 </B>and <B>401 </B>. OTG Vbus charge-discharge control is 
applied at input <B>500 </B>. With input <B>500 </B>low, transistor <B>506 
</B>turns ON and drives charge/discharge node <B>502 </B>to approximately 5.0 
volts. This is referred to as the quick charge state where capacitor <B>512 
</B>is quickly charged to approximately 5.0 volts. When node <B>500 </B>switches 
high transistor <B>506 </B>turns OFF and transistor <B>508 </B>turns ON. Node 
<B>502 </B>is driven to the discharge state via the discharge path through 
resistor <B>507 </B>and ON transistor <B>508 </B>. The discharge timing is 
controlled by the values of resistor <B>507 </B>and capacitor <B>512 </B>. 
Resistors <B>504 </B>, <B>505 </B>and <B>509 </B>control the drive paths for 
transistors <B>506 </B>and <B>508 </B>. Comparator <B>511 </B>continuously 
compares the voltage level on the Vbus node <B>501 </B>to that of the 
charge-discharge node <B>502 </B>. </P>
<P>As charge/discharge node <B>502 </B>discharges to a low, voltage comparator 
<B>511 </B>drives output node <B>503 </B>to a high the as long as Vbus less than 
5.0 volts. When the circuit transitions from quick charge to discharge the 
voltage at charge/discharge node <B>502 </B>ramps downward to below Vbus, the 
voltage at output node <B>503 </B>switches from high to low. </P>
<P>The key point of this circuit is that the discharge rate for capacitor <B>512 
</B>is programmed as data into the microcontroller. This allows the timing on 
OTG Vbus Detect <B>503 </B>to be translated by the microcontroller to an 
equivalent Vbus voltage measurement. The microcontroller is programmed to make 
decisions, based on this Vbus measurement, as to whether the amplitude/timing on 
Vbus meet the Vbus detect requirements. The circuit is used both for detecting 
that the external B-Device is pulsing and that an external A-Device has 
powered-down. Thus, the OTG Vbus Pulsing Detect circuit implements a 
software-controlled mixed signal circuit discharge and quick-charge circuit to 
detect Vbus activity in SRP and HNP. </P>
<P>FIG. 6 illustrates the OTG Vbus pulsing circuits <B>302 </B>and <B>402 </B>. 
When input <B>600 </B>is driven high transistor <B>604 </B>turns ON. Current 
drive from 3.3 volts supply <B>610 </B>is limited by resistor <B>603 </B>and 
charges capacitor <B>605 </B>through transistor <B>604 </B>. When input <B>600 
</B>is driven low, transistor <B>604 </B>turns OFF and capacitor <B>605 
</B>discharges through resistor <B>601 </B>in series with resistor <B>602 </B>. 
This circuit provides pulsing at Vbus output <B>606 </B>of sufficient energy to 
signal the B-Device that it is receiving Vbus pulsing from the A-Device to 
denote a valid SRP request. </P>
<P>FIG. 7 illustrates the dataline pulsing circuits <B>304 </B>and <B>404 </B>. 
When input <B>700 </B>is driven low transistor <B>703 </B>turns ON through 
resistor <B>702 </B>. Current drive through <B>703 </B>and resistor <B>702 
</B>provides active pull-up action at the D+ line <B>706 </B>. When line <B>700 
</B>is driven high OTG dataline pulsing ceases. </P>
<P>FIG. 8 illustrates the dataline pull-down circuits <B>303 </B>and <B>403 
</B>. For D+, when input <B>800 </B>is driven high transistor <B>804 </B>turns 
ON through resistor <B>803 </B>. Current drive through <B>804 </B>and resistor 
<B>803 </B>provides active pull-down of D+ line <B>805 </B>. When input <B>800 
</B>is driven low OTG D+ dataline pull-down is disabled. Resistors <B>801 
</B>and <B>802 </B>form a voltage divider for input drive to the gate of 
transistor <B>804 </B>. </P>
<P>Similarly for D−, when input <B>811 </B>is driven high transistor <B>809 
</B>turns ON through resistor <B>808 </B>. Current drive through <B>809 </B>and 
resistor <B>808 </B>provides active pull-down of D−line <B>810 </B>. When input 
<B>811 </B>is driven low OTG D− dataline pull-down is disabled. Resistors <B>806 
</B>and <B>807 </B>form a voltage divider for input drive to the gate of 
transistor <B>804 </B>. </P>
<P>The USB power management circuits for blocks <B>306 </B>of FIG. 3 and 406 of 
FIG. 4 are illustrated in FIG. 9. The 5.0 volts source <B>903 </B>from the 
microcontroller is fed to the source of PMOS power switch transistor <B>904 
</B>. PWR CTL <B>900 </B>provides power control for activating or powering down 
the Vbus supply <B>906 </B>. When PWR CTL <B>900 </B>is low transistor <B>904 
</B>turns ON, charges bypass capacitor <B>905 </B>and powers up Vbus <B>906 
</B>. When the microcontroller drives PWR CTL <B>900 </B>high, transistor <B>904 
</B>turns OFF and Vbus is powered down. Vbus discharges through paths in the 
connecting circuitry. Resistors <B>901 </B>and <B>902 </B>form a voltage divider 
to generate gate input voltage for transistor <B>904 </B>. </P><?DETDESC description="Detailed Description" end="tail"?></DIV></DIV><BR 
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