clk16x.v

来自「带有自适应功能的UART」· Verilog 代码 · 共 103 行

module  clk16x(clk,rst,Din,clk16x);
  input  clk,rst;
  input  Din;
  output  clk16x;
  
  reg  start,finish;
  reg  finish1,finish2,Din1,Din2;
  reg  clk16x;
  
  reg[1:0] counter_start;
  reg[2:0] counter_finish;
  reg[15:0] counter_clk,div,counter_div;
  
  always@(posedge clk or posedge rst)
    if(rst)
      begin
        Din1<=1'b1;
        Din2<=1'b1;
      end
    else
      begin
        Din1<=Din;
        Din2<=Din1;
      end
  
  always@(posedge clk or posedge rst)
    if(rst)
      start<=1'b0;
    else if(!start && !finish && Din1 && !Din2)
      start<=1'b1;
    else if(counter_start>=2'b10 && start)
      start<=1'b0;
      
  always@(posedge rst or posedge Din1)
    if(rst)
      counter_start<=2'b0;
    else if(start)
      counter_start<=counter_start+1;
      
  always@(posedge clk or posedge rst)
    if(rst)
      finish<=1'b0;
    else if(counter_finish>=3'b100 && !finish)
      finish<=1'b1;
      
  always@(posedge rst or negedge Din2)
    if(rst)
      counter_finish<=3'b0;
    else if(!finish)
      counter_finish<=counter_finish+1;
      
  always@(posedge clk or posedge rst)
    if(rst)
      counter_clk<=16'b0;
    else if(start)
      counter_clk<=counter_clk+1;
      

      
   always@(posedge clk or posedge rst)
    if(rst)
      begin
        div<=16'b0;
        finish1<=1'b0;
        finish2<=1'b0;
      end
    else
      begin
        finish1<=finish;
        finish2<=finish1;
        if(finish1 && !finish2)
          div<=counter_clk>>3'b111;
       end
            

  
  always @ (posedge clk or posedge rst)
   begin
    if(rst)
      begin
        counter_div<=16'b1;
        clk16x<=1'b0;
      end
    else 
      if(finish)
      begin
        if(counter_div<div)
          begin
          counter_div<=counter_div+16'b1;
          end
        else
          begin
            counter_div<=16'b1;
            clk16x<=~clk16x;
          end
      end
      else
         counter_div<=16'b0;
  end
endmodule