📄 main.lst
字号:
00000052 4800 LDR R0,=input_buffer ; input_buffer
00000054 2108 MOV R1,#0x8
00000056 F7FF BL SPI_read?T ; T=0x0001 (1)
00000058 FFD3 BL SPI_read?T ; T=0x0001 (2)
36: IOCLR0 = input_buffer[0];
0000005C 4800 LDR R0,=input_buffer ; input_buffer
0000005E 7800 LDRB R0,[R0,#0x0] ; input_buffer
00000060 1C01 MOV R1,R0
00000062 4800 LDR R0,=0xE002800C
00000064 6001 STR R1,[R0,#0x0]
41: }
00000066 L_5:
00000066 E7FE B L_5 ; T=0x00000066
00000068 ; SCOPE-END
00000068 B002 ADD R13,#0x8
0000006A BC08 POP {R3}
0000006C 4718 BX R3
0000006E ENDP ; 'main'
*** CODE SEGMENT '?PR?SPI_write?T?main':
45: void SPI_write(unsigned char *buffer,unsigned char bytecount)
00000000 ---- Variable 'bytecount' assigned to Register 'R1' ----
00000000 ---- Variable 'buffer' assigned to Register 'R0' ----
47: lock = 1;
00000000 2301 MOV R3,#0x1
00000002 4800 LDR R2,=lock ; lock
00000004 7013 STRB R3,[R2,#0x0] ; lock
48: SPI_buffer = buffer;
00000006 4800 LDR R2,=SPI_buffer ; SPI_buffer
ARM COMPILER V2.00f, main 20/02/05 12:49:03 PAGE 6
00000008 6010 STR R0,[R2,#0x0] ; buffer
49: SPI_bytecount = bytecount;
0000000A 4800 LDR R0,=SPI_bytecount ; SPI_bytecount
0000000C 7001 STRB R1,[R0,#0x0] ; bytecount
50: IOCLR0 = 0x00000400; //Pull Chipselect low
0000000E 4800 LDR R1,=0x400
00000010 4800 LDR R0,=0xE002800C
00000012 6001 STR R1,[R0,#0x0]
51: S0SPDR = 0x00000006; //Send WRITE opcode
00000014 2106 MOV R1,#0x6
00000016 4800 LDR R0,=0xE0020008
00000018 7001 STRB R1,[R0,#0x0]
52: status = 0x01; //set next state
0000001A 2101 MOV R1,#0x1
0000001C 4800 LDR R0,=status ; status
0000001E 7001 STRB R1,[R0,#0x0] ; status
53: }
00000020 4770 BX R14
00000022 ENDP ; 'SPI_write?T'
*** CODE SEGMENT '?PR?SPI_read?T?main':
55: void SPI_read(unsigned char *buffer,unsigned char bytecount)
00000000 ---- Variable 'bytecount' assigned to Register 'R1' ----
00000000 ---- Variable 'buffer' assigned to Register 'R0' ----
57: SPI_buffer = buffer;
00000000 4800 LDR R2,=SPI_buffer ; SPI_buffer
00000002 6010 STR R0,[R2,#0x0] ; buffer
58: SPI_bytecount = bytecount;
00000004 4800 LDR R0,=SPI_bytecount ; SPI_bytecount
00000006 7001 STRB R1,[R0,#0x0] ; bytecount
59: IOCLR0 = 0x00000400; //Pull Chipselect low
00000008 4800 LDR R1,=0x400
0000000A 4800 LDR R0,=0xE002800C
0000000C 6001 STR R1,[R0,#0x0]
60: S0SPDR = 0x00000003; //Send READ code
0000000E 2103 MOV R1,#0x3
00000010 4800 LDR R0,=0xE0020008
00000012 7001 STRB R1,[R0,#0x0]
61: status = 0x05; //set next state
00000014 2105 MOV R1,#0x5
00000016 4800 LDR R0,=status ; status
00000018 7001 STRB R1,[R0,#0x0] ; status
62: }
0000001A 4770 BX R14
0000001C ENDP ; 'SPI_read?T'
*** CODE SEGMENT '?PR?SPI_ISR?A?main':
65: void SPI_ISR (void) __irq
00000000 E92D0007 STMDB R13!,{R0-R2}
66: {
00000004 ; SCOPE-START
70: switch(status)
00000004 E5100000 LDR R0,=status ; status
00000008 E5D00000 LDRB R0,[R0,#0x0] ; status
0000000C E1A01000 MOV R1,R0
00000010 E2511002 SUBS R1,R1,#0x0002
00000014 0A000012 BEQ L_12 ; Targ=0x64
00000018 E2511001 SUBS R1,R1,#0x0001
0000001C 0A000017 BEQ L_13 ; Targ=0x80
00000020 E2511001 SUBS R1,R1,#0x0001
00000024 0A00002A BEQ L_14 ; Targ=0xD4
00000028 E2511001 SUBS R1,R1,#0x0001
0000002C 0A000032 BEQ L_15 ; Targ=0xFC
00000030 E2511001 SUBS R1,R1,#0x0001
00000034 0A000037 BEQ L_16 ; Targ=0x118
00000038 E2511001 SUBS R1,R1,#0x0001
0000003C 0A00004F BEQ L_17 ; Targ=0x180
00000040 E2911006 ADDS R1,R1,#0x0006
ARM COMPILER V2.00f, main 20/02/05 12:49:03 PAGE 7
00000044 1A000050 BNE L_9 ; Targ=0x18C
72: case (0x01):
00000048 L_10:
74: S0SPDR = 0x00000002;
00000048 E3A01002 MOV R1,#0x2
0000004C E5100000 LDR R0,=0xE0020008
00000050 E5C01000 STRB R1,[R0,#0x0]
75: status = 0x02; //set next state
00000054 E3A01002 MOV R1,#0x2
00000058 E5100000 LDR R0,=status ; status
0000005C E5C01000 STRB R1,[R0,#0x0] ; status
76: break;
00000060 EA000049 B L_9 ; Targ=0x18C
78: case (0x02): //Send Write Address
00000064 L_12:
79: S0SPDR = 0x00000000;
00000064 E3A01000 MOV R1,#0x0
00000068 E5100000 LDR R0,=0xE0020008
0000006C E5C01000 STRB R1,[R0,#0x0]
80: status = 0x03; //Set next state
00000070 E3A01003 MOV R1,#0x3
00000074 E5100000 LDR R0,=status ; status
00000078 E5C01000 STRB R1,[R0,#0x0] ; status
81: break;
0000007C EA000042 B L_9 ; Targ=0x18C
83: case (0x03): //write data
00000080 L_13:
84: S0SPDR = *SPI_buffer++;
00000080 E5101000 LDR R1,=SPI_buffer ; SPI_buffer
00000084 E5910000 LDR R0,[R1,#0x0] ; SPI_buffer
00000088 E2802001 ADD R2,R0,#0x0001
0000008C E5812000 STR R2,[R1,#0x0] ; SPI_buffer
00000090 E5D01000 LDRB R1,[R0,#0x0]
00000094 E5100000 LDR R0,=0xE0020008
00000098 E5C01000 STRB R1,[R0,#0x0]
85: if( --SPI_bytecount)
0000009C E5101000 LDR R1,=SPI_bytecount ; SPI_bytecount
000000A0 E5D10000 LDRB R0,[R1,#0x0] ; SPI_bytecount
000000A4 E2400001 SUB R0,R0,#0x0001
000000A8 E5C10000 STRB R0,[R1,#0x0] ; SPI_bytecount
000000AC E3500000 CMP R0,#0x0000
000000B0 0A000003 BEQ L_18 ; Targ=0xC4
87: status = 0x03; //Set Next state
000000B4 E3A01003 MOV R1,#0x3
000000B8 E5100000 LDR R0,=status ; status
000000BC E5C01000 STRB R1,[R0,#0x0] ; status
88: }
000000C0 EA000031 B L_9 ; Targ=0x18C
000000C4 L_18:
91: status = 0x04; //End condition
000000C4 E3A01004 MOV R1,#0x4
000000C8 E5100000 LDR R0,=status ; status
000000CC E5C01000 STRB R1,[R0,#0x0] ; status
93: break;
000000D0 EA00002D B L_9 ; Targ=0x18C
95: case (0x04): //End condition
000000D4 L_14:
96: S0SPDR = 0x00000055; //Need this dummy write for simulation
000000D4 E3A01055 MOV R1,#0x55
000000D8 E5100000 LDR R0,=0xE0020008
000000DC E5C01000 STRB R1,[R0,#0x0]
97: IOSET0 = 0x00000400; //Pull Chipselect high
000000E0 E3A01B01 MOV R1,#0x400
000000E4 E5100000 LDR R0,=0xE0028004
000000E8 E5801000 STR R1,[R0,#0x0]
98: status = 0x07; //jump to null case
ARM COMPILER V2.00f, main 20/02/05 12:49:03 PAGE 8
000000EC E3A01007 MOV R1,#0x7
000000F0 E5100000 LDR R0,=status ; status
000000F4 E5C01000 STRB R1,[R0,#0x0] ; status
99: break;
000000F8 EA000023 B L_9 ; Targ=0x18C
102: case (0x05):
000000FC L_15:
103: S0SPDR = 0x00000000; //Send Address
000000FC E3A01000 MOV R1,#0x0
00000100 E5100000 LDR R0,=0xE0020008
00000104 E5C01000 STRB R1,[R0,#0x0]
104: status = 0x06; //set next state
00000108 E3A01006 MOV R1,#0x6
0000010C E5100000 LDR R0,=status ; status
00000110 E5C01000 STRB R1,[R0,#0x0] ; status
105: break;
00000114 EA00001C B L_9 ; Targ=0x18C
107: case (0x06):
00000118 L_16:
108: *SPI_buffer = S0SPDR; //read data
00000118 E5100000 LDR R0,=0xE0020008
0000011C E5D01000 LDRB R1,[R0,#0x0]
00000120 E5100000 LDR R0,=SPI_buffer ; SPI_buffer
00000124 E5900000 LDR R0,[R0,#0x0] ; SPI_buffer
00000128 E5C01000 STRB R1,[R0,#0x0]
109: S0SPDR = 0xFF; //Send Address
0000012C E3A010FF MOV R1,#0xFF
00000130 E5100000 LDR R0,=0xE0020008
00000134 E5C01000 STRB R1,[R0,#0x0]
110: SPI_buffer++;
00000138 E5100000 LDR R0,=SPI_buffer ; SPI_buffer
0000013C E5901000 LDR R1,[R0,#0x0] ; SPI_buffer
00000140 E2811001 ADD R1,R1,#0x0001
00000144 E5801000 STR R1,[R0,#0x0] ; SPI_buffer
112: if( --SPI_bytecount)
00000148 E5101000 LDR R1,=SPI_bytecount ; SPI_bytecount
0000014C E5D10000 LDRB R0,[R1,#0x0] ; SPI_bytecount
00000150 E2400001 SUB R0,R0,#0x0001
00000154 E5C10000 STRB R0,[R1,#0x0] ; SPI_bytecount
00000158 E3500000 CMP R0,#0x0000
0000015C 0A000003 BEQ L_20 ; Targ=0x170
114: status = 0x06; //Set Next state
00000160 E3A01006 MOV R1,#0x6
00000164 E5100000 LDR R0,=status ; status
00000168 E5C01000 STRB R1,[R0,#0x0] ; status
115: }
0000016C EA000006 B L_9 ; Targ=0x18C
00000170 L_20:
118: status = 0x07; //End condition
00000170 E3A01007 MOV R1,#0x7
00000174 E5100000 LDR R0,=status ; status
00000178 E5C01000 STRB R1,[R0,#0x0] ; status
120: break;
0000017C EA000002 B L_9 ; Targ=0x18C
122: case (0x07) : //Null Case
00000180 L_17:
123: lock = 0;
00000180 E3A01000 MOV R1,#0x0
00000184 E5100000 LDR R0,=lock ; lock
00000188 E5C01000 STRB R1,[R0,#0x0] ; lock
129: }
0000018C L_9:
131: S0SPINT = 0x01; //Signal end of interrupt
0000018C E3A01001 MOV R1,#0x1
00000190 E5100000 LDR R0,=0xE002001C
00000194 E5C01000 STRB R1,[R0,#0x0]
ARM COMPILER V2.00f, main 20/02/05 12:49:03 PAGE 9
132: VICVectAddr = 0x00000000; //Dummy write to signal end of interrupt
00000198 E3A01000 MOV R1,#0x0
0000019C E5100000 LDR R0,=0xFFFFF030
000001A0 E5801000 STR R1,[R0,#0x0]
000001A4 ; SCOPE-END
000001A4 E8BD0007 LDMIA R13!,{R0-R2}
000001A8 E25EF004 SUBS R15,R14,#0x0004
000001AC ENDP ; 'SPI_ISR?A'
Module Information Static
----------------------------------
code size = ------
data size = 15
const size = 8
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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