📄 main.lst
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ARM COMPILER V2.00f, main 20/02/05 09:46:16 PAGE 1
ARM COMPILER V2.00f, COMPILATION OF MODULE main
OBJECT MODULE PLACED IN main.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe main.c THUMB OPTIMIZE(7,SPEED) BROWSE DEBUG TABS(4)
stmt level source
1 /************************************************************/
2 /* PROJECT NAME: PLL */
3 /* Project: LPC2100 Training course */
4 /* Engineer: T Martin tmartin@hitex.co.uk */
5 /* Filename: main.c */
6 /* Language: C */
7 /* Compiler: Keil ARM V2.00b */
8 /* Assembler: */
9 /* */
10 /************************************************************/
11 /* COPYRIGHT: Hitex UK Ltd 2005 */
12 /* LICENSE: THIS VERSION CREATED FOR FREE DISTRIBUTION */
13 /************************************************************/
14 /* Function: */
15 /* */
16 /* Example Phase locked loop configuration for LPC2100 */
17 /* */
18 /* Demonstrates setup of PLL and VPB divider */
19 /* */
20 /* Oscillator frequency 12.000 Mhz */
21 /* Target board keil MCB21000 */
22 /************************************************************/
23
24 #include <LPC210x.H>
25
26 void init_PLL(void);
27
28
29 int main(void)
30 {
31 1 init_PLL(); // Configure the PLL and VPB divider
32 1 //This is normally done in the startup code
33 1 //but for this example the startup config is disabled
34 1 while(1) //main loop
35 1 {
36 2 ; //Idle
37 2 }
38 1 }
39
40
41 void init_PLL(void)
42 {
43 1 PLLCFG = 0x00000024; // Set multiplier and divider of PLL to give 60.00 Mhz
44 1 PLLCON = 0x00000001; // Enable the PLL
45 1
46 1 PLLFEED = 0x000000AA; // Update PLL registers with feed sequence
47 1 PLLFEED = 0x00000055;
48 1
49 1 while (!(PLLSTAT & 0x00000400)) // test Lock bit
50 1 {
51 2 ;
52 2 }
53 1 PLLCON = 0x00000003; // Connect the PLL
54 1
55 1 PLLFEED = 0x000000AA; //Update PLL registers
56 1 PLLFEED = 0x00000055;
57 1
58 1 VPBDIV = 0x00000002; //Set the VLSI peripheral bus to 30.000Mhz
59 1 }
ARM COMPILER V2.00f, main 20/02/05 09:46:16 PAGE 2
60
ARM COMPILER V2.00f, main 20/02/05 09:46:16 PAGE 3
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN NUMBER (__startup)
*** PUBLICS:
PUBLIC init_PLL?T
PUBLIC main
*** CODE SEGMENT '?PR?main?main':
29: int main(void)
00000000 B500 PUSH {LR}
31: init_PLL(); // Configure the PLL and VPB divider
00000002 F7FF BL init_PLL?T ; T=0x0001 (1)
00000004 FFFD BL init_PLL?T ; T=0x0001 (2)
37: }
00000008 L_1:
00000008 E7FE B L_1 ; T=0x00000008
0000000A BC08 POP {R3}
0000000C 4718 BX R3
0000000E ENDP ; 'main'
*** CODE SEGMENT '?PR?init_PLL?T?main':
43: PLLCFG = 0x00000024; // Set multiplier and divider of PLL to give 60.00 Mhz
00000000 2124 MOV R1,#0x24
00000002 4800 LDR R0,=0xE01FC084
00000004 7001 STRB R1,[R0,#0x0]
44: PLLCON = 0x00000001; // Enable the PLL
00000006 2101 MOV R1,#0x1
00000008 4800 LDR R0,=0xE01FC080
0000000A 7001 STRB R1,[R0,#0x0]
46: PLLFEED = 0x000000AA; // Update PLL registers with feed sequence
0000000C 21AA MOV R1,#0xAA
0000000E 4800 LDR R0,=0xE01FC08C
00000010 7001 STRB R1,[R0,#0x0]
47: PLLFEED = 0x00000055;
00000012 2155 MOV R1,#0x55
00000014 4800 LDR R0,=0xE01FC08C
00000016 7001 STRB R1,[R0,#0x0]
52: }
00000018 L_5:
00000018 4800 LDR R0,=0xE01FC088
0000001A 8800 LDRH R0,[R0,#0x0]
0000001C 4800 LDR R1,=0x400
0000001E 4208 TST R0,R1
00000020 D0FA BEQ L_5 ; T=0x00000018
53: PLLCON = 0x00000003; // Connect the PLL
00000022 2103 MOV R1,#0x3
00000024 4800 LDR R0,=0xE01FC080
00000026 7001 STRB R1,[R0,#0x0]
55: PLLFEED = 0x000000AA; //Update PLL registers
00000028 21AA MOV R1,#0xAA
0000002A 4800 LDR R0,=0xE01FC08C
0000002C 7001 STRB R1,[R0,#0x0]
56: PLLFEED = 0x00000055;
0000002E 2155 MOV R1,#0x55
00000030 4800 LDR R0,=0xE01FC08C
00000032 7001 STRB R1,[R0,#0x0]
58: VPBDIV = 0x00000002; //Set the VLSI peripheral bus to 30.000Mhz
00000034 2102 MOV R1,#0x2
00000036 4800 LDR R0,=0xE01FC100
00000038 7001 STRB R1,[R0,#0x0]
59: }
0000003A 4770 BX R14
0000003C ENDP ; 'init_PLL?T'
ARM COMPILER V2.00f, main 20/02/05 09:46:16 PAGE 4
Module Information Static
----------------------------------
code size = ------
data size = ------
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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