📄 trialfinal.mdl
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Block {
BlockType RelationalOperator
Operator ">="
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LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
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LogicDataType "uint(8)"
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Block {
BlockType Selector
InputType "Vector"
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RowSrc "Internal"
Rows "1"
ColumnSrc "Internal"
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RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
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RTWMemSecDataParameters "Inherit from model"
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FontName "Arial"
FontSize 10
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FontWeight "normal"
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Name "trialfinal"
Location [2, 78, 1278, 750]
Open on
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ModelBrowserWidth 200
ScreenColor "white"
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PaperType "usletter"
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ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "AWGN\nChannel"
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Position [545, 116, 640, 174]
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SourceType "AWGN Channel"
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SystemSampleTime "-1"
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RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
seed "61"
noiseMode "Signal to noise ratio (Es/No)"
EbNodB "1"
EsNodB "13"
SNRdB "10"
bitsPerSym "1"
Ps "1000"
Tsym "4/7"
variance "10"
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Block {
BlockType Reference
Name "BPSK\nDemodulator\nBaseband"
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Position [660, 61, 735, 109]
SourceBlock "commdigbbndpm3/BPSK\nDemodulator\nBaseband"
SourceType "BPSK Demodulator Baseband"
ShowPortLabels on
SystemSampleTime "-1"
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RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ph "0"
outDtype "double"
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Block {
BlockType Reference
Name "BPSK\nModulator\nBaseband"
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SourceBlock "commdigbbndpm3/BPSK\nModulator\nBaseband"
SourceType "BPSK Modulator Baseband"
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SystemSampleTime "-1"
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RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ph "0"
outDtype "double"
outWordLen "16"
outUDDataType "sfix(16)"
outFracLenMode "Best precision"
outFracLen "15"
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Block {
BlockType Reference
Name "Bernoulli Binary\nGenerator1"
Ports [0, 1]
Position [95, 43, 175, 87]
DialogController "commDDGCreate"
DialogControllerArgs "DataTag0"
SourceBlock "commrandsrc2/Bernoulli Binary\nGenerator"
SourceType "Bernoulli Binary Generator"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
P "0.6"
seed "61"
Ts "1"
frameBased on
sampPerFrame "4"
orient off
outDataType "double"
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Block {
BlockType Reference
Name "Binary\nCyclic Decoder"
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Position [760, 163, 840, 207]
SourceBlock "commblkcod2/Binary\nCyclic Decoder"
SourceType "Binary Cyclic Decoder"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
n "7"
p "4"
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Block {
BlockType Reference
Name "Binary\nCyclic Encoder"
Ports [1, 1]
Position [285, 43, 365, 87]
SourceBlock "commblkcod2/Binary\nCyclic Encoder"
SourceType "Binary Cyclic Encoder"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
n "7"
p "4"
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BlockType Display
Name "Display"
Ports [1]
Position [245, 159, 360, 261]
Decimation "1"
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BlockType Display
Name "Display1"
Ports [1]
Position [880, 32, 1040, 268]
Decimation "1"
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Block {
BlockType Display
Name "Display2"
Ports [1]
Position [450, 355, 590, 565]
Decimation "1"
Lockdown off
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Block {
BlockType Display
Name "Display4"
Ports [1]
Position [950, 331, 1045, 459]
Decimation "1"
Lockdown off
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Block {
BlockType Reference
Name "Error Rate\nCalculation"
Ports [2, 1]
Position [715, 292, 790, 343]
SourceBlock "commsink2/Error Rate\nCalculation"
SourceType "Error Rate Calculation"
N "0"
st_delay "0"
cp_mode "Entire frame"
subframe "[]"
PMode "Port"
WsName "ErrorVec"
RsMode2 off
stop off
numErr "100"
maxBits "1e7"
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Line {
SrcBlock "Bernoulli Binary\nGenerator1"
SrcPort 1
Points [25, 0; 0, 35]
Branch {
Points [0, -35]
DstBlock "Binary\nCyclic Encoder"
DstPort 1
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Branch {
Points [0, 110]
Branch {
DstBlock "Display"
DstPort 1
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Branch {
Points [0, 120]
DstBlock "Error Rate\nCalculation"
DstPort 2
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Line {
SrcBlock "Binary\nCyclic Encoder"
SrcPort 1
Points [25, 0; 0, 25; 20, 0]
Branch {
DstBlock "BPSK\nModulator\nBaseband"
DstPort 1
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Branch {
Points [20, 0]
DstBlock "Display2"
DstPort 1
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Line {
SrcBlock "BPSK\nDemodulator\nBaseband"
SrcPort 1
Points [20, 0; 0, 45; -25, 0; 0, 55]
DstBlock "Binary\nCyclic Decoder"
DstPort 1
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Line {
SrcBlock "BPSK\nModulator\nBaseband"
SrcPort 1
Points [5, 0; 0, 55]
DstBlock "AWGN\nChannel"
DstPort 1
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Line {
SrcBlock "AWGN\nChannel"
SrcPort 1
DstBlock "BPSK\nDemodulator\nBaseband"
DstPort 1
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Line {
SrcBlock "Error Rate\nCalculation"
SrcPort 1
Points [55, 0; 0, 75]
DstBlock "Display4"
DstPort 1
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Line {
SrcBlock "Binary\nCyclic Decoder"
SrcPort 1
Points [0, 30]
Branch {
Points [0, 55; -145, 0]
DstBlock "Error Rate\nCalculation"
DstPort 1
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Branch {
Points [10, 0; 0, -65]
DstBlock "Display1"
DstPort 1
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Data " %)30 . > 8 ( 0 % "
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