📄 rtmp_init.c
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========================================================================*/NDIS_STATUS NICInitializeAdapter( IN PRTMP_ADAPTER pAd, IN BOOLEAN bHardReset){ NDIS_STATUS Status = NDIS_STATUS_SUCCESS; WPDMA_GLO_CFG_STRUC GloCfg;// INT_MASK_CSR_STRUC IntMask; ULONG i =0, j=0; AC_TXOP_CSR0_STRUC csr0; DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitializeAdapter\n")); // 3. Set DMA global configuration except TX_DMA_EN and RX_DMA_EN bits:retry: i = 0; do { RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word); if ((GloCfg.field.TxDMABusy == 0) && (GloCfg.field.RxDMABusy == 0)) break; RTMPusecDelay(1000); i++; }while ( i<100); DBGPRINT(RT_DEBUG_TRACE, ("<== DMA offset 0x208 = 0x%x\n", GloCfg.word)); GloCfg.word &= 0xff0; GloCfg.field.EnTXWriteBackDDONE =1; RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word); // Record HW Beacon offset pAd->BeaconOffset[0] = HW_BEACON_BASE0; pAd->BeaconOffset[1] = HW_BEACON_BASE1; pAd->BeaconOffset[2] = HW_BEACON_BASE2; pAd->BeaconOffset[3] = HW_BEACON_BASE3; pAd->BeaconOffset[4] = HW_BEACON_BASE4; pAd->BeaconOffset[5] = HW_BEACON_BASE5; pAd->BeaconOffset[6] = HW_BEACON_BASE6; pAd->BeaconOffset[7] = HW_BEACON_BASE7; // // write all shared Ring's base address into ASIC // // asic simulation sequence put this ahead before loading firmware. // pbf hardware reset // Initialze ASIC for TX & Rx operation if (NICInitializeAsic(pAd , bHardReset) != NDIS_STATUS_SUCCESS) { if (j++ == 0) { NICLoadFirmware(pAd); goto retry; } return NDIS_STATUS_FAILURE; } // WMM parameter csr0.word = 0; RTMP_IO_WRITE32(pAd, WMM_TXOP0_CFG, csr0.word); if (pAd->CommonCfg.PhyMode == PHY_11B) { csr0.field.Ac0Txop = 192; // AC_VI: 192*32us ~= 6ms csr0.field.Ac1Txop = 96; // AC_VO: 96*32us ~= 3ms } else { csr0.field.Ac0Txop = 96; // AC_VI: 96*32us ~= 3ms csr0.field.Ac1Txop = 48; // AC_VO: 48*32us ~= 1.5ms } RTMP_IO_WRITE32(pAd, WMM_TXOP1_CFG, csr0.word); // reset action // Load firmware // Status = NICLoadFirmware(pAd); DBGPRINT(RT_DEBUG_TRACE, ("<-- NICInitializeAdapter\n")); return Status;}/* ======================================================================== Routine Description: Initialize ASIC Arguments: Adapter Pointer to our adapter Return Value: None IRQL = PASSIVE_LEVEL Note: ========================================================================*/NDIS_STATUS NICInitializeAsic( IN PRTMP_ADAPTER pAd, IN BOOLEAN bHardReset){ ULONG Index = 0; UCHAR R0 = 0xff; UINT32 MacCsr12 = 0, Counter = 0;#ifdef RTMP_MAC_USB UINT32 MacCsr0 = 0; NTSTATUS Status; UCHAR Value = 0xff;#endif // RTMP_MAC_USB // USHORT KeyIdx; INT i,apidx; DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitializeAsic\n"));#ifdef RTMP_MAC_USB // // Make sure MAC gets ready after NICLoadFirmware(). // Index = 0; //To avoid hang-on issue when interface up in kernel 2.4, //we use a local variable "MacCsr0" instead of using "pAd->MACVersion" directly. do { RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0); if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF)) break; RTMPusecDelay(10); } while (Index++ < 100); pAd->MACVersion = MacCsr0; DBGPRINT(RT_DEBUG_TRACE, ("MAC_CSR0 [ Ver:Rev=0x%08x]\n", pAd->MACVersion)); // turn on bit13 (set to zero) after rt2860D. This is to solve high-current issue. RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &MacCsr12); MacCsr12 &= (~0x2000); RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, MacCsr12); RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x3); RTMP_IO_WRITE32(pAd, USB_DMA_CFG, 0x0); Status = RTUSBVenderReset(pAd); RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0); // Initialize MAC register to default value for(Index=0; Index<NUM_MAC_REG_PARMS; Index++) { RTMP_IO_WRITE32(pAd, (USHORT)MACRegTable[Index].Register, MACRegTable[Index].Value); }#ifdef CONFIG_STA_SUPPORT IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { for (Index = 0; Index < NUM_STA_MAC_REG_PARMS; Index++) { RTMP_IO_WRITE32(pAd, (USHORT)STAMACRegTable[Index].Register, STAMACRegTable[Index].Value); } }#endif // CONFIG_STA_SUPPORT //#endif // RTMP_MAC_USB // // // Before program BBP, we need to wait BBP/RF get wake up. // Index = 0; do { RTMP_IO_READ32(pAd, MAC_STATUS_CFG, &MacCsr12); if ((MacCsr12 & 0x03) == 0) // if BB.RF is stable break; DBGPRINT(RT_DEBUG_TRACE, ("Check MAC_STATUS_CFG = Busy = %x\n", MacCsr12)); RTMPusecDelay(1000); } while (Index++ < 100); // The commands to firmware should be after these commands, these commands will init firmware // PCI and USB are not the same because PCI driver needs to wait for PCI bus ready RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, 0); // initialize BBP R/W access agent RTMP_IO_WRITE32(pAd, H2M_MAILBOX_CSR, 0); RTMPusecDelay(1000); // Read BBP register, make sure BBP is up and running before write new data Index = 0; do { RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R0, &R0); DBGPRINT(RT_DEBUG_TRACE, ("BBP version = %x\n", R0)); } while ((++Index < 20) && ((R0 == 0xff) || (R0 == 0x00))); //ASSERT(Index < 20); //this will cause BSOD on Check-build driver if ((R0 == 0xff) || (R0 == 0x00)) return NDIS_STATUS_FAILURE; // Initialize BBP register to default value for (Index = 0; Index < NUM_BBP_REG_PARMS; Index++) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBPRegTable[Index].Register, BBPRegTable[Index].Value); } // for rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT. // RT3090 should not program BBP R84 to 0x19, otherwise TX will block. if (((pAd->MACVersion & 0xffff) != 0x0101) && (!IS_RT30xx(pAd))) RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19); if (pAd->MACVersion == 0x28600100) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x12); } if (pAd->MACVersion >= RALINK_2880E_VERSION && pAd->MACVersion < RALINK_3070_VERSION) // 3*3 { // enlarge MAX_LEN_CFG UINT32 csr; RTMP_IO_READ32(pAd, MAX_LEN_CFG, &csr); csr &= 0xFFF; csr |= 0x2000; RTMP_IO_WRITE32(pAd, MAX_LEN_CFG, csr); }#ifdef RTMP_MAC_USB{ UCHAR MAC_Value[]={0xff,0xff,0xff,0xff,0xff,0xff,0xff,0,0}; //Initialize WCID table Value = 0xff; for(Index =0 ;Index < 254;Index++) { RTUSBMultiWrite(pAd, (USHORT)(MAC_WCID_BASE + Index * 8), MAC_Value, 8); }}#endif // RTMP_MAC_USB //#ifdef CONFIG_STA_SUPPORT // Add radio off control IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { if (pAd->StaCfg.bRadio == FALSE) {// RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x00001818); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF); DBGPRINT(RT_DEBUG_TRACE, ("Set Radio Off\n")); } }#endif // CONFIG_STA_SUPPORT // // Clear raw counters RTMP_IO_READ32(pAd, RX_STA_CNT0, &Counter); RTMP_IO_READ32(pAd, RX_STA_CNT1, &Counter); RTMP_IO_READ32(pAd, RX_STA_CNT2, &Counter); RTMP_IO_READ32(pAd, TX_STA_CNT0, &Counter); RTMP_IO_READ32(pAd, TX_STA_CNT1, &Counter); RTMP_IO_READ32(pAd, TX_STA_CNT2, &Counter); // ASIC will keep garbage value after boot // Clear all shared key table when initial // This routine can be ignored in radio-ON/OFF operation. if (bHardReset) { for (KeyIdx = 0; KeyIdx < 4; KeyIdx++) { RTMP_IO_WRITE32(pAd, SHARED_KEY_MODE_BASE + 4*KeyIdx, 0); } // Clear all pairwise key table when initial for (KeyIdx = 0; KeyIdx < 256; KeyIdx++) { RTMP_IO_WRITE32(pAd, MAC_WCID_ATTRIBUTE_BASE + (KeyIdx * HW_WCID_ATTRI_SIZE), 1); } } // assert HOST ready bit// RTMP_IO_WRITE32(pAd, MAC_CSR1, 0x0); // 2004-09-14 asked by Mark// RTMP_IO_WRITE32(pAd, MAC_CSR1, 0x4); // It isn't necessary to clear this space when not hard reset. if (bHardReset == TRUE) { // clear all on-chip BEACON frame space for (apidx = 0; apidx < HW_BEACON_MAX_COUNT; apidx++) { for (i = 0; i < HW_BEACON_OFFSET>>2; i+=4) RTMP_IO_WRITE32(pAd, pAd->BeaconOffset[apidx] + i, 0x00); } } #ifdef RTMP_MAC_USB AsicDisableSync(pAd); // Clear raw counters RTMP_IO_READ32(pAd, RX_STA_CNT0, &Counter); RTMP_IO_READ32(pAd, RX_STA_CNT1, &Counter); RTMP_IO_READ32(pAd, RX_STA_CNT2, &Counter); RTMP_IO_READ32(pAd, TX_STA_CNT0, &Counter); RTMP_IO_READ32(pAd, TX_STA_CNT1, &Counter); RTMP_IO_READ32(pAd, TX_STA_CNT2, &Counter); // Default PCI clock cycle per ms is different as default setting, which is based on PCI. RTMP_IO_READ32(pAd, USB_CYC_CFG, &Counter); Counter&=0xffffff00; Counter|=0x000001e; RTMP_IO_WRITE32(pAd, USB_CYC_CFG, Counter);#endif // RTMP_MAC_USB //#ifdef CONFIG_STA_SUPPORT IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { // for rt2860E and after, init TXOP_CTRL_CFG with 0x583f. This is for extension channel overlapping IOT. if ((pAd->MACVersion&0xffff) != 0x0101) RTMP_IO_WRITE32(pAd, TXOP_CTRL_CFG, 0x583f); }#endif // CONFIG_STA_SUPPORT // DBGPRINT(RT_DEBUG_TRACE, ("<-- NICInitializeAsic\n")); return NDIS_STATUS_SUCCESS;}/* ======================================================================== Routine Description: Reset NIC Asics Arguments: Adapter Pointer to our adapter Return Value: None IRQL = PASSIVE_LEVEL Note: Reset NIC to initial state AS IS system boot up time. ========================================================================*/VOID NICIssueReset( IN PRTMP_ADAPTER pAd){ UINT32 Value = 0; DBGPRINT(RT_DEBUG_TRACE, ("--> NICIssueReset\n")); // Abort Tx, prevent ASIC from writing to Host memory //RTMP_IO_WRITE32(pAd, TX_CNTL_CSR, 0x001f0000); // Disable Rx, register value supposed will remain after reset RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value); Value &= (0xfffffff3); RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value); // Issue reset and clear from reset state RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x03); // 2004-09-17 change from 0x01 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x00); DBGPRINT(RT_DEBUG_TRACE, ("<-- NICIssueReset\n"));}/* ======================================================================== Routine Description: Check ASIC registers and find any reason the system might hang Arguments: Adapter Pointer to our adapter Return Value: None IRQL = DISPATCH_LEVEL ========================================================================*/BOOLEAN NICCheckForHang( IN PRTMP_ADAPTER pAd){ return (FALSE);}VOID NICUpdateFifoStaCounters( IN PRTMP_ADAPTER pAd){ TX_STA_FIFO_STRUC StaFifo; MAC_TABLE_ENTRY *pEntry; UCHAR i = 0; UCHAR pid = 0, wcid = 0; CHAR reTry; UCHAR succMCS;#ifdef RALINK_ATE /* Nothing to do in ATE mode */ if (ATE_ON(pAd)) return;#endif // RALINK_ATE // do { RTMP_IO_READ32(pAd, TX_STA_FIFO, &StaFifo.word); if (StaFifo.field.bValid == 0) break; wcid = (UCHAR)StaFifo.field.wcid; /* ignore NoACK and MGMT frame use 0xFF as WCID */ if ((StaFifo.field.TxAckRequired == 0) || (wcid >= MAX_LEN_OF_MAC_TABLE)) { i++; continue; } /* PID store Tx MCS Rate */ pid = (UCHAR)StaFifo.field.PidType; pEntry = &pAd->MacTab.Content[wcid]; pEntry->DebugFIFOCount++;#ifdef DOT11_N_SUPPORT
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