rtmp_mac.h

ralink 2870 usb无线网卡 最新驱动

	struct	{
		UINT32       Bss0Key0CipherAlg:3;
		UINT32       :1;
		UINT32       Bss0Key1CipherAlg:3;
		UINT32       :1;
		UINT32       Bss0Key2CipherAlg:3;
		UINT32       :1;
		UINT32       Bss0Key3CipherAlg:3;
		UINT32       :1;
		UINT32       Bss1Key0CipherAlg:3;
		UINT32       :1;
		UINT32       Bss1Key1CipherAlg:3;
		UINT32       :1;
		UINT32       Bss1Key2CipherAlg:3;
		UINT32       :1;
		UINT32       Bss1Key3CipherAlg:3;
		UINT32       :1;
	}	field;
	UINT32			word;
}	SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
#endif
// 64-entry for pairwise key table
typedef struct _HW_WCID_ENTRY {  // 8-byte per entry
    UCHAR   Address[6];
    UCHAR   Rsv[2];
} HW_WCID_ENTRY, PHW_WCID_ENTRY;


// =================================================================================
// WCID  format
// =================================================================================
//7.1	WCID  ENTRY  format  : 8bytes
typedef	struct	_WCID_ENTRY_STRUC {
	UCHAR		RXBABitmap7;    // bit0 for TID8, bit7 for TID 15
	UCHAR		RXBABitmap0;    // bit0 for TID0, bit7 for TID 7
	UCHAR		MAC[6];	// 0 for shared key table.  1 for pairwise key table
}	WCID_ENTRY_STRUC, *PWCID_ENTRY_STRUC;

//8.1.1	SECURITY  KEY  format  : 8DW
// 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table
typedef struct _HW_KEY_ENTRY {          // 32-byte per entry
    UCHAR   Key[16];
    UCHAR   TxMic[8];
    UCHAR   RxMic[8];
} HW_KEY_ENTRY, *PHW_KEY_ENTRY; 

//8.1.2	IV/EIV  format  : 2DW

//8.1.3	RX attribute entry format  : 1DW
#ifdef RT_BIG_ENDIAN
typedef	struct	_MAC_ATTRIBUTE_STRUC {
	UINT32		rsv:22;
	UINT32		RXWIUDF:3;
	UINT32		BSSIDIdx:3; //multipleBSS index for the WCID
	UINT32		PairKeyMode:3;
	UINT32		KeyTab:1;	// 0 for shared key table.  1 for pairwise key table
}	MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
#else
typedef	struct	_MAC_ATTRIBUTE_STRUC {
	UINT32		KeyTab:1;	// 0 for shared key table.  1 for pairwise key table
	UINT32		PairKeyMode:3;
	UINT32		BSSIDIdx:3; //multipleBSS index for the WCID
	UINT32		RXWIUDF:3;
	UINT32		rsv:22;
}	MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
#endif


// =================================================================================
// HOST-MCU communication data structure
// =================================================================================

//
// H2M_MAILBOX_CSR: Host-to-MCU Mailbox
//
#ifdef RT_BIG_ENDIAN
typedef union  _H2M_MAILBOX_STRUC {
    struct {
        UINT32       Owner:8;
        UINT32       CmdToken:8;    // 0xff tells MCU not to report CmdDoneInt after excuting the command
        UINT32       HighByte:8;
        UINT32       LowByte:8;
    }   field;
    UINT32           word;
} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
#else
typedef union  _H2M_MAILBOX_STRUC {
    struct {
        UINT32       LowByte:8;
        UINT32       HighByte:8;
        UINT32       CmdToken:8;
        UINT32       Owner:8;
    }   field;
    UINT32           word;
} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
#endif

//
// M2H_CMD_DONE_CSR: MCU-to-Host command complete indication
//
#ifdef RT_BIG_ENDIAN
typedef union _M2H_CMD_DONE_STRUC {
    struct  {
        UINT32       CmdToken3;
        UINT32       CmdToken2;
        UINT32       CmdToken1;
        UINT32       CmdToken0;
    } field;
    UINT32           word;
} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
#else
typedef union _M2H_CMD_DONE_STRUC {
    struct  {
        UINT32       CmdToken0;
        UINT32       CmdToken1;
        UINT32       CmdToken2;
        UINT32       CmdToken3;
    } field;
    UINT32           word;
} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
#endif


//NAV_TIME_CFG :NAV
#ifdef RT_BIG_ENDIAN
typedef	union	_NAV_TIME_CFG_STRUC	{
	struct	{
		USHORT		rsv:6;   
		USHORT		ZeroSifs:1;               // Applied zero SIFS timer after OFDM RX 0: disable
		USHORT		Eifs:9;               // in unit of 1-us
		UCHAR       SlotTime;    // in unit of 1-us
		UCHAR		Sifs;               // in unit of 1-us
	}	field;
	UINT32			word;
}	NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
#else
typedef	union	_NAV_TIME_CFG_STRUC	{
	struct	{
		UCHAR		Sifs;               // in unit of 1-us
		UCHAR       SlotTime;    // in unit of 1-us
		USHORT		Eifs:9;               // in unit of 1-us
		USHORT		ZeroSifs:1;               // Applied zero SIFS timer after OFDM RX 0: disable
		USHORT		rsv:6;             
	}	field;
	UINT32			word;
}	NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
#endif


//
// RX_FILTR_CFG:  /RX configuration register
//
#ifdef RT_BIG_ENDIAN
typedef	union	RX_FILTR_CFG_STRUC	{
	struct	{
		UINT32		:15;		
		UINT32       DropRsvCntlType:1;

        	UINT32       	DropBAR:1;       //  
		UINT32		DropBA:1;		//  
		UINT32		DropPsPoll:1;		// Drop Ps-Poll
		UINT32		DropRts:1;		// Drop Ps-Poll

		UINT32		DropCts:1;		// Drop Ps-Poll
		UINT32		DropAck:1;		// Drop Ps-Poll
		UINT32		DropCFEnd:1;		// Drop Ps-Poll
		UINT32		DropCFEndAck:1;		// Drop Ps-Poll

		UINT32		DropDuplicate:1;		// Drop duplicate frame
		UINT32		DropBcast:1;		// Drop broadcast frames
		UINT32		DropMcast:1;		// Drop multicast frames
		UINT32		DropVerErr:1;	    // Drop version error frame

		UINT32		DropNotMyBSSID:1;			// Drop fram ToDs bit is true
		UINT32		DropNotToMe:1;		// Drop not to me unicast frame
		UINT32		DropPhyErr:1;		// Drop physical error
		UINT32		DropCRCErr:1;		// Drop CRC error
	}	field;
	UINT32			word;
}	RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
#else
typedef	union	_RX_FILTR_CFG_STRUC	{
	struct	{
		UINT32		DropCRCErr:1;		// Drop CRC error
		UINT32		DropPhyErr:1;		// Drop physical error
		UINT32		DropNotToMe:1;		// Drop not to me unicast frame
		UINT32		DropNotMyBSSID:1;			// Drop fram ToDs bit is true

		UINT32		DropVerErr:1;	    // Drop version error frame
		UINT32		DropMcast:1;		// Drop multicast frames
		UINT32		DropBcast:1;		// Drop broadcast frames
		UINT32		DropDuplicate:1;		// Drop duplicate frame

		UINT32		DropCFEndAck:1;		// Drop Ps-Poll
		UINT32		DropCFEnd:1;		// Drop Ps-Poll
		UINT32		DropAck:1;		// Drop Ps-Poll
		UINT32		DropCts:1;		// Drop Ps-Poll

		UINT32		DropRts:1;		// Drop Ps-Poll
		UINT32		DropPsPoll:1;		// Drop Ps-Poll
		UINT32		DropBA:1;		//  
        	UINT32       	DropBAR:1;       //  

		UINT32       	DropRsvCntlType:1;
		UINT32		:15;
	}	field;
	UINT32			word;
}	RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
#endif




//
// PHY_CSR4: RF serial control register
//
#ifdef RT_BIG_ENDIAN
typedef	union	_PHY_CSR4_STRUC	{
	struct	{
		UINT32		Busy:1;				// 1: ASIC is busy execute RF programming.		
		UINT32		PLL_LD:1;			// RF PLL_LD status
		UINT32		IFSelect:1;			// 1: select IF	to program,	0: select RF to	program
		UINT32		NumberOfBits:5;		// Number of bits used in RFRegValue (I:20,	RFMD:22)
		UINT32		RFRegValue:24;		// Register	value (include register	id)	serial out to RF/IF	chip.
	}	field;
	UINT32			word;
}	PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
#else
typedef	union	_PHY_CSR4_STRUC	{
	struct	{
		UINT32		RFRegValue:24;		// Register	value (include register	id)	serial out to RF/IF	chip.
		UINT32		NumberOfBits:5;		// Number of bits used in RFRegValue (I:20,	RFMD:22)
		UINT32		IFSelect:1;			// 1: select IF	to program,	0: select RF to	program
		UINT32		PLL_LD:1;			// RF PLL_LD status
		UINT32		Busy:1;				// 1: ASIC is busy execute RF programming.
	}	field;
	UINT32			word;
}	PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
#endif


//
// SEC_CSR5: shared key table security mode register
//
#ifdef RT_BIG_ENDIAN
typedef	union	_SEC_CSR5_STRUC	{
	struct	{
        UINT32       :1;
        UINT32       Bss3Key3CipherAlg:3;
        UINT32       :1;
        UINT32       Bss3Key2CipherAlg:3;
        UINT32       :1;
        UINT32       Bss3Key1CipherAlg:3;
        UINT32       :1;
        UINT32       Bss3Key0CipherAlg:3;
        UINT32       :1;
        UINT32       Bss2Key3CipherAlg:3;
        UINT32       :1;
        UINT32       Bss2Key2CipherAlg:3;
        UINT32       :1;
        UINT32       Bss2Key1CipherAlg:3;
        UINT32       :1;
        UINT32       Bss2Key0CipherAlg:3;
	}	field;
	UINT32			word;
}	SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
#else
typedef	union	_SEC_CSR5_STRUC	{
	struct	{
        UINT32       Bss2Key0CipherAlg:3;
        UINT32       :1;
        UINT32       Bss2Key1CipherAlg:3;
        UINT32       :1;
        UINT32       Bss2Key2CipherAlg:3;
        UINT32       :1;
        UINT32       Bss2Key3CipherAlg:3;
        UINT32       :1;
        UINT32       Bss3Key0CipherAlg:3;
        UINT32       :1;
        UINT32       Bss3Key1CipherAlg:3;
        UINT32       :1;
        UINT32       Bss3Key2CipherAlg:3;
        UINT32       :1;
        UINT32       Bss3Key3CipherAlg:3;
        UINT32       :1;
	}	field;
	UINT32			word;
}	SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
#endif


//
// HOST_CMD_CSR: For HOST to interrupt embedded processor
//
#ifdef RT_BIG_ENDIAN
typedef	union	_HOST_CMD_CSR_STRUC	{
	struct	{
	    UINT32   Rsv:24;
	    UINT32   HostCommand:8;
	}	field;
	UINT32			word;
}	HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
#else
typedef	union	_HOST_CMD_CSR_STRUC	{
	struct	{
	    UINT32   HostCommand:8;
	    UINT32   Rsv:24;
	}	field;
	UINT32			word;
}	HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
#endif


//
// AIFSN_CSR: AIFSN for each EDCA AC
//



//
// E2PROM_CSR: EEPROM control register
//
#ifdef RT_BIG_ENDIAN
typedef	union	_E2PROM_CSR_STRUC	{
	struct	{
		UINT32		Rsvd:25;
		UINT32       LoadStatus:1;   // 1:loading, 0:done
		UINT32		Type:1;			// 1: 93C46, 0:93C66
		UINT32		EepromDO:1;
		UINT32		EepromDI:1;
		UINT32		EepromCS:1;
		UINT32		EepromSK:1;
		UINT32		Reload:1;		// Reload EEPROM content, write one to reload, self-cleared.
	}	field;
	UINT32			word;
}	E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
#else
typedef	union	_E2PROM_CSR_STRUC	{
	struct	{
		UINT32		Reload:1;		// Reload EEPROM content, write one to reload, self-cleared.
		UINT32		EepromSK:1;
		UINT32		EepromCS:1;
		UINT32		EepromDI:1;
		UINT32		EepromDO:1;
		UINT32		Type:1;			// 1: 93C46, 0:93C66
		UINT32       LoadStatus:1;   // 1:loading, 0:done
		UINT32		Rsvd:25;
	}	field;
	UINT32			word;
}	E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
#endif

//
// QOS_CSR0: TXOP holder address0 register
//
#ifdef RT_BIG_ENDIAN
typedef	union	_QOS_CSR0_STRUC	{
	struct	{
		UCHAR		Byte3;		// MAC address byte 3
		UCHAR		Byte2;		// MAC address byte 2
		UCHAR		Byte1;		// MAC address byte 1
		UCHAR		Byte0;		// MAC address byte 0
	}	field;
	UINT32			word;
}	QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
#else
typedef	union	_QOS_CSR0_STRUC	{
	struct	{
		UCHAR		Byte0;		// MAC address byte 0
		UCHAR		Byte1;		// MAC address byte 1
		UCHAR		Byte2;		// MAC address byte 2
		UCHAR		Byte3;		// MAC address byte 3
	}	field;
	UINT32			word;
}	QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
#endif

//
// QOS_CSR1: TXOP holder address1 register
//
#ifdef RT_BIG_ENDIAN
typedef	union	_QOS_CSR1_STRUC	{
	struct	{
		UCHAR		Rsvd1;
		UCHAR		Rsvd0;
		UCHAR		Byte5;		// MAC address byte 5
		UCHAR		Byte4;		// MAC address byte 4
	}	field;
	UINT32			word;
}	QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
#else
typedef	union	_QOS_CSR1_STRUC	{
	struct	{
		UCHAR		Byte4;		// MAC address byte 4
		UCHAR		Byte5;		// MAC address byte 5
		UCHAR		Rsvd0;
		UCHAR		Rsvd1;
	}	field;
	UINT32			word;
}	QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
#endif

#define	RF_CSR_CFG	0x500
#ifdef RT_BIG_ENDIAN
typedef	union	_RF_CSR_CFG_STRUC	{
	struct	{
		UINT	Rsvd1:14;				// Reserved
		UINT	RF_CSR_KICK:1;			// kick RF register read/write
		UINT	RF_CSR_WR:1;			// 0: read  1: write
		UINT	Rsvd2:3;				// Reserved
		UINT	TESTCSR_RFACC_REGNUM:5;	// RF register ID
		UINT	RF_CSR_DATA:8;			// DATA
	}	field;
	UINT	word;
}	RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
#else
typedef	union	_RF_CSR_CFG_STRUC	{
	struct	{
		UINT	RF_CSR_DATA:8;			// DATA 
		UINT	TESTCSR_RFACC_REGNUM:5;	// RF register ID
		UINT	Rsvd2:3;				// Reserved
		UINT	RF_CSR_WR:1;			// 0: read  1: write
		UINT	RF_CSR_KICK:1;			// kick RF register read/write
		UINT	Rsvd1:14;				// Reserved
	}	field;
	UINT	word;
}	RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
#endif


//
// Other on-chip shared memory space, base = 0x2000