rtmp_mac.h

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	    UINT32  CckmSifsTime:8;        //  unit 1us. Applied after CCK RX/TX
	    UINT32  OfdmSifsTime:8;        //  unit 1us. Applied after OFDM RX/TX
	    UINT32  OfdmXifsTime:4;        //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
	    UINT32  EIFS:9;        //  unit 1us
	    UINT32  BBRxendEnable:1;        //  reference RXEND signal to begin XIFS defer
	    UINT32  rsv:2;         
	}	field;
	UINT32			word;
}	IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
#endif

#define BKOFF_SLOT_CFG             0x1104		 //  mac_csr9 last 8 bits
#define NAV_TIME_CFG             0x1108		 // NAV  (MAC_CSR15)
#define CH_TIME_CFG             0x110C		 	// Count as channel busy 
#define PBF_LIFE_TIMER             0x1110		 //TX/RX MPDU timestamp timer (free run)Unit: 1us  
#define BCN_TIME_CFG             0x1114		 // TXRX_CSR9

#define BCN_OFFSET0				0x042C
#define BCN_OFFSET1				0x0430

//
// BCN_TIME_CFG : Synchronization control register
//
#ifdef RT_BIG_ENDIAN
typedef	union	_BCN_TIME_CFG_STRUC	{
	struct	{
		UINT32		TxTimestampCompensate:8;
        UINT32       :3;
		UINT32		bBeaconGen:1;		// Enable beacon generator
        UINT32       bTBTTEnable:1;
		UINT32		TsfSyncMode:2;		// Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
		UINT32		bTsfTicking:1;		// Enable TSF auto counting
		UINT32       BeaconInterval:16;  // in unit of 1/16 TU
	}	field;
	UINT32			word;
}	BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
#else
typedef	union	_BCN_TIME_CFG_STRUC	{
	struct	{
		UINT32       BeaconInterval:16;  // in unit of 1/16 TU
		UINT32		bTsfTicking:1;		// Enable TSF auto counting
		UINT32		TsfSyncMode:2;		// Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
        UINT32       bTBTTEnable:1;
		UINT32		bBeaconGen:1;		// Enable beacon generator
        UINT32       :3;
		UINT32		TxTimestampCompensate:8;
	}	field;
	UINT32			word;
}	BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
#endif
#define TBTT_SYNC_CFG            0x1118  		// txrx_csr10
#define TSF_TIMER_DW0             0x111C  		// Local TSF timer lsb 32 bits. Read-only
#define TSF_TIMER_DW1             0x1120  		// msb 32 bits. Read-only.
#define TBTT_TIMER             	0x1124  		// TImer remains till next TBTT. Read-only.  TXRX_CSR14
#define INT_TIMER_CFG              	0x1128  		//  
#define INT_TIMER_EN             	0x112c  		//  GP-timer and pre-tbtt Int enable
#define CH_IDLE_STA              	0x1130  		//  channel idle time
#define CH_BUSY_STA              	0x1134  		//  channle busy time
//
//  4.2 MAC POWER  configuration registers (offset:0x1200)
//
#define MAC_STATUS_CFG             0x1200		 // old MAC_CSR12
#define PWR_PIN_CFG             0x1204		 // old MAC_CSR12
#define AUTO_WAKEUP_CFG             0x1208		 // old MAC_CSR10
//
// AUTO_WAKEUP_CFG: Manual power control / status register 
//
#ifdef RT_BIG_ENDIAN
typedef	union	_AUTO_WAKEUP_STRUC	{
	struct	{
		UINT32		:16;
		UINT32		EnableAutoWakeup:1;	// 0:sleep, 1:awake
		UINT32       NumofSleepingTbtt:7;          // ForceWake has high privilege than PutToSleep when both set
		UINT32       AutoLeadTime:8;
	}	field;
	UINT32			word;
}	AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
#else
typedef	union	_AUTO_WAKEUP_STRUC	{
	struct	{
		UINT32       AutoLeadTime:8;
		UINT32       NumofSleepingTbtt:7;          // ForceWake has high privilege than PutToSleep when both set
		UINT32		EnableAutoWakeup:1;	// 0:sleep, 1:awake
		UINT32		:16;
	}	field;
	UINT32			word;
}	AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
#endif
//
//  4.3 MAC TX  configuration registers (offset:0x1300)
//       

#define EDCA_AC0_CFG	0x1300		//AC_TXOP_CSR0 0x3474
#define EDCA_AC1_CFG	0x1304
#define EDCA_AC2_CFG	0x1308
#define EDCA_AC3_CFG	0x130c
#ifdef RT_BIG_ENDIAN
typedef	union	_EDCA_AC_CFG_STRUC	{
	struct	{
	    UINT32  :12;        // 
	    UINT32  Cwmax:4;        //unit power of 2
	    UINT32  Cwmin:4;        // 
	    UINT32  Aifsn:4;        // # of slot time
	    UINT32  AcTxop:8;        //  in unit of 32us
	}	field;
	UINT32			word;
}	EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
#else
typedef	union	_EDCA_AC_CFG_STRUC	{
	struct	{
	    UINT32  AcTxop:8;        //  in unit of 32us
	    UINT32  Aifsn:4;        // # of slot time
	    UINT32  Cwmin:4;        // 
	    UINT32  Cwmax:4;        //unit power of 2
	    UINT32  :12;       // 
	}	field;
	UINT32			word;
}	EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
#endif

#define EDCA_TID_AC_MAP	0x1310
#define TX_PWR_CFG_0	0x1314
#define TX_PWR_CFG_1	0x1318
#define TX_PWR_CFG_2	0x131C
#define TX_PWR_CFG_3	0x1320
#define TX_PWR_CFG_4	0x1324
#define TX_PIN_CFG		0x1328		 
#define TX_BAND_CFG	0x132c		// 0x1 use upper 20MHz. 0 juse lower 20MHz
#define TX_SW_CFG0		0x1330
#define TX_SW_CFG1		0x1334
#define TX_SW_CFG2		0x1338
#define TXOP_THRES_CFG		0x133c
#define TXOP_CTRL_CFG		0x1340
#define TX_RTS_CFG		0x1344

#ifdef RT_BIG_ENDIAN
typedef	union	_TX_RTS_CFG_STRUC	{
	struct	{
	    UINT32       rsv:7;     
	    UINT32       RtsFbkEn:1;    // enable rts rate fallback
	    UINT32       RtsThres:16;    // unit:byte
	    UINT32       AutoRtsRetryLimit:8;
	}	field;
	UINT32			word;
}	TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
#else
typedef	union	_TX_RTS_CFG_STRUC	{
	struct	{
	    UINT32       AutoRtsRetryLimit:8;
	    UINT32       RtsThres:16;    // unit:byte
	    UINT32       RtsFbkEn:1;    // enable rts rate fallback
	    UINT32       rsv:7;     // 1: HT non-STBC control frame enable
	}	field;
	UINT32			word;
}	TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
#endif
#define TX_TIMEOUT_CFG	0x1348
#ifdef RT_BIG_ENDIAN
typedef	union	_TX_TIMEOUT_CFG_STRUC	{
	struct	{
	    UINT32       rsv2:8;     
	    UINT32       TxopTimeout:8;	//TXOP timeout value for TXOP truncation.  It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
	    UINT32       RxAckTimeout:8;	// unit:slot. Used for TX precedure
	    UINT32       MpduLifeTime:4;    //  expiration time = 2^(9+MPDU LIFE TIME)  us
	    UINT32       rsv:4;     
	}	field;
	UINT32			word;
}	TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
#else
typedef	union	_TX_TIMEOUT_CFG_STRUC	{
	struct	{
	    UINT32       rsv:4;     
	    UINT32       MpduLifeTime:4;    //  expiration time = 2^(9+MPDU LIFE TIME)  us
	    UINT32       RxAckTimeout:8;	// unit:slot. Used for TX precedure
	    UINT32       TxopTimeout:8;	//TXOP timeout value for TXOP truncation.  It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
	    UINT32       rsv2:8;     // 1: HT non-STBC control frame enable
	}	field;
	UINT32			word;
}	TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
#endif
#define TX_RTY_CFG	0x134c
#ifdef RT_BIG_ENDIAN
typedef	union PACKED _TX_RTY_CFG_STRUC	{
	struct	{
	    UINT32       rsv:1;     
	    UINT32       TxautoFBEnable:1;    // Tx retry PHY rate auto fallback enable
	    UINT32       AggRtyMode:1;	// Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
	    UINT32       NonAggRtyMode:1;	// Non-Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
	    UINT32       LongRtyThre:12;	// Long retry threshoold
	    UINT32       LongRtyLimit:8;	//long retry limit
	    UINT32       ShortRtyLimit:8;	//  short retry limit
	    
	}	field;
	UINT32			word;
}	TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
#else
typedef	union PACKED _TX_RTY_CFG_STRUC	{
	struct	{
	    UINT32       ShortRtyLimit:8;	//  short retry limit
	    UINT32       LongRtyLimit:8;	//long retry limit
	    UINT32       LongRtyThre:12;	// Long retry threshoold
	    UINT32       NonAggRtyMode:1;	// Non-Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
	    UINT32       AggRtyMode:1;	// Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
	    UINT32       TxautoFBEnable:1;    // Tx retry PHY rate auto fallback enable
	    UINT32       rsv:1;     // 1: HT non-STBC control frame enable
	}	field;
	UINT32			word;
}	TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
#endif
#define TX_LINK_CFG	0x1350
#ifdef RT_BIG_ENDIAN
typedef	union	PACKED _TX_LINK_CFG_STRUC	{
	struct PACKED {
	    UINT32       RemotMFS:8;	//remote MCS feedback sequence number     
	    UINT32       RemotMFB:8;    //  remote MCS feedback
	    UINT32       rsv:3;	//  
	    UINT32       TxCFAckEn:1;	//   Piggyback CF-ACK enable
	    UINT32       TxRDGEn:1;	// RDG TX enable 
	    UINT32       TxMRQEn:1;	//  MCS request TX enable
	    UINT32       RemoteUMFSEnable:1;	//  remote unsolicit  MFB enable.  0: not apply remote remote unsolicit (MFS=7)
	    UINT32       MFBEnable:1;	//  TX apply remote MFB 1:enable
	    UINT32       RemoteMFBLifeTime:8;	//remote MFB life time. unit : 32us
	}	field;
	UINT32			word;
}	TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
#else
typedef	union	PACKED _TX_LINK_CFG_STRUC	{
	struct PACKED {
	    UINT32       RemoteMFBLifeTime:8;	//remote MFB life time. unit : 32us
	    UINT32       MFBEnable:1;	//  TX apply remote MFB 1:enable
	    UINT32       RemoteUMFSEnable:1;	//  remote unsolicit  MFB enable.  0: not apply remote remote unsolicit (MFS=7)
	    UINT32       TxMRQEn:1;	//  MCS request TX enable
	    UINT32       TxRDGEn:1;	// RDG TX enable 
	    UINT32       TxCFAckEn:1;	//   Piggyback CF-ACK enable
	    UINT32       rsv:3;	//  
	    UINT32       RemotMFB:8;    //  remote MCS feedback
	    UINT32       RemotMFS:8;	//remote MCS feedback sequence number     
	}	field;
	UINT32			word;
}	TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
#endif
#define HT_FBK_CFG0	0x1354
#ifdef RT_BIG_ENDIAN
typedef	union PACKED _HT_FBK_CFG0_STRUC	{
	struct	{
	    UINT32       HTMCS7FBK:4;
	    UINT32       HTMCS6FBK:4;
	    UINT32       HTMCS5FBK:4;
	    UINT32       HTMCS4FBK:4;
	    UINT32       HTMCS3FBK:4;
	    UINT32       HTMCS2FBK:4;
	    UINT32       HTMCS1FBK:4;
	    UINT32       HTMCS0FBK:4;
	}	field;
	UINT32			word;
}	HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
#else
typedef	union PACKED _HT_FBK_CFG0_STRUC	{
	struct	{
	    UINT32       HTMCS0FBK:4;
	    UINT32       HTMCS1FBK:4;
	    UINT32       HTMCS2FBK:4;
	    UINT32       HTMCS3FBK:4;
	    UINT32       HTMCS4FBK:4;
	    UINT32       HTMCS5FBK:4;
	    UINT32       HTMCS6FBK:4;
	    UINT32       HTMCS7FBK:4;
	}	field;
	UINT32			word;
}	HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
#endif
#define HT_FBK_CFG1	0x1358
#ifdef RT_BIG_ENDIAN
typedef	union	_HT_FBK_CFG1_STRUC	{
	struct	{
	    UINT32       HTMCS15FBK:4;
	    UINT32       HTMCS14FBK:4;
	    UINT32       HTMCS13FBK:4;
	    UINT32       HTMCS12FBK:4;
	    UINT32       HTMCS11FBK:4;
	    UINT32       HTMCS10FBK:4;
	    UINT32       HTMCS9FBK:4;
	    UINT32       HTMCS8FBK:4;
	}	field;
	UINT32			word;
}	HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
#else
typedef	union	_HT_FBK_CFG1_STRUC	{
	struct	{
	    UINT32       HTMCS8FBK:4;
	    UINT32       HTMCS9FBK:4;
	    UINT32       HTMCS10FBK:4;
	    UINT32       HTMCS11FBK:4;
	    UINT32       HTMCS12FBK:4;
	    UINT32       HTMCS13FBK:4;
	    UINT32       HTMCS14FBK:4;
	    UINT32       HTMCS15FBK:4;
	}	field;
	UINT32			word;
}	HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
#endif
#define LG_FBK_CFG0	0x135c
#ifdef RT_BIG_ENDIAN
typedef	union	_LG_FBK_CFG0_STRUC	{
	struct	{
	    UINT32       OFDMMCS7FBK:4;	//initial value is 6
	    UINT32       OFDMMCS6FBK:4;	//initial value is 5
	    UINT32       OFDMMCS5FBK:4;	//initial value is 4
	    UINT32       OFDMMCS4FBK:4;	//initial value is 3
	    UINT32       OFDMMCS3FBK:4;	//initial value is 2
	    UINT32       OFDMMCS2FBK:4;	//initial value is 1
	    UINT32       OFDMMCS1FBK:4;	//initial value is 0
	    UINT32       OFDMMCS0FBK:4;	//initial value is 0
	}	field;
	UINT32			word;
}	LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
#else
typedef	union	_LG_FBK_CFG0_STRUC	{
	struct	{
	    UINT32       OFDMMCS0FBK:4;	//initial value is 0
	    UINT32       OFDMMCS1FBK:4;	//initial value is 0
	    UINT32       OFDMMCS2FBK:4;	//initial value is 1
	    UINT32       OFDMMCS3FBK:4;	//initial value is 2
	    UINT32       OFDMMCS4FBK:4;	//initial value is 3
	    UINT32       OFDMMCS5FBK:4;	//initial value is 4
	    UINT32       OFDMMCS6FBK:4;	//initial value is 5
	    UINT32       OFDMMCS7FBK:4;	//initial value is 6
	}	field;
	UINT32			word;
}	LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
#endif
#define LG_FBK_CFG1		0x1360
#ifdef RT_BIG_ENDIAN
typedef	union	_LG_FBK_CFG1_STRUC	{
	struct	{
	    UINT32       rsv:16;	 
	    UINT32       CCKMCS3FBK:4;	//initial value is 2
	    UINT32       CCKMCS2FBK:4;	//initial value is 1
	    UINT32       CCKMCS1FBK:4;	//initial value is 0
	    UINT32       CCKMCS0FBK:4;	//initial value is 0
	}	field;
	UINT32			word;
}	LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
#else
typedef	union	_LG_FBK_CFG1_STRUC	{
	struct	{
	    UINT32       CCKMCS0FBK:4;	//initial value is 0
	    UINT32       CCKMCS1FBK:4;	//initial value is 0
	    UINT32       CCKMCS2FBK:4;	//initial value is 1
	    UINT32       CCKMCS3FBK:4;	//initial value is 2
	    UINT32       rsv:16;	 
	}	field;
	UINT32			word;
}	LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
#endif


//=======================================================
//================ Protection Paramater================================
//=======================================================
#define CCK_PROT_CFG	0x1364		//CCK Protection
#define ASIC_SHORTNAV		1
#define ASIC_LONGNAV		2
#define ASIC_RTS		1
#define ASIC_CTS		2
#ifdef RT_BIG_ENDIAN
typedef	union	_PROT_CFG_STRUC	{
	struct	{
	    UINT32       rsv:5;	 
	    UINT32       RTSThEn:1;	//RTS threshold enable on CCK TX
	    UINT32       TxopAllowGF40:1;	//CCK TXOP allowance.0:disallow.
	    UINT32       TxopAllowGF20:1;	//CCK TXOP allowance.0:disallow.
	    UINT32       TxopAllowMM40:1;	//CCK TXOP allowance.0:disallow.
	    UINT32       TxopAllowMM20:1;	//CCK TXOP allowance. 0:disallow.
	    UINT32       TxopAllowOfdm:1;	//CCK TXOP allowance.0:disallow.
	    UINT32       TxopAllowCck:1;	//CCK TXOP allowance.0:disallow.
	    UINT32       ProtectNav:2;	//TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect,  2:LongNAVProtect, 3:rsv
	    UINT32       ProtectCtrl:2;	//Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
	    UINT32       ProtectRate:16;	//Protection control frame rate for CCK TX(RTS/CTS/CFEnd). 
	}	field;
	UINT32			word;
}	PROT_CFG_STRUC, *PPROT_CFG_STRUC;
#else
typedef	union	_PROT_CFG_STRUC	{
	struct	{
	    UINT32       ProtectRate:16;	//Protection control frame rate for CCK TX(RTS/CTS/CFEnd). 
	    UINT32       ProtectCtrl:2;	//Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
	    UINT32       ProtectNav:2;	//TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect,  2:LongNAVProtect, 3:rsv
	    UINT32       TxopAllowCck:1;	//CCK TXOP allowance.0:disallow.
	    UINT32       TxopAllowOfdm:1;	//CCK TXOP allowance.0:disallow.
	    UINT32       TxopAllowMM20:1;	//CCK TXOP allowance. 0:disallow.
	    UINT32       TxopAllowMM40:1;	//CCK TXOP allowance.0:disallow.
	    UINT32       TxopAllowGF20:1;	//CCK TXOP allowance.0:disallow.
	    UINT32       TxopAllowGF40:1;	//CCK TXOP allowance.0:disallow.
	    UINT32       RTSThEn:1;	//RTS threshold enable on CCK TX
	    UINT32       rsv:5;	 
	}	field;
	UINT32			word;
}	PROT_CFG_STRUC, *PPROT_CFG_STRUC;
#endif

#define OFDM_PROT_CFG	0x1368		//OFDM Protection
#define MM20_PROT_CFG	0x136C		//MM20 Protection
#define MM40_PROT_CFG	0x1370		//MM40 Protection
#define GF20_PROT_CFG	0x1374		//GF20 Protection
#define GF40_PROT_CFG	0x1378		//GR40 Protection
#define EXP_CTS_TIME	0x137C		// 
#define EXP_ACK_TIME	0x1380		// 

//
//  4.4 MAC RX configuration registers (offset:0x1400)
//
#define RX_FILTR_CFG	0x1400			//TXRX_CSR0
#define AUTO_RSP_CFG	0x1404			//TXRX_CSR4
//
// TXRX_CSR4: Auto-Responder/
//
#ifdef RT_BIG_ENDIAN
typedef union _AUTO_RSP_CFG_STRUC {
 struct {
     UINT32        :24;    
     UINT32       AckCtsPsmBit:1;   // Power bit value in conrtrol frame
     UINT32       DualCTSEn:1;   // Power bit value in conrtrol frame
     UINT32       rsv:1;   // Power bit value in conrtrol frame
     UINT32       AutoResponderPreamble:1;    // 0:long, 1:short preamble
     UINT32       CTS40MRef:1;  // Response CTS 40MHz duplicate mode
     UINT32       CTS40MMode:1;  // Response CTS 40MHz duplicate mode
     UINT32       BACAckPolicyEnable:1;    // 0:long, 1:short preamble
     UINT32       AutoResponderEnable:1;
 } field;
 UINT32   word;
} AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
#else
typedef union _AUTO_RSP_CFG_STRUC {
 struct {
     UINT32       AutoResponderEnable:1;
     UINT32       BACAckPolicyEnable:1;    // 0:long, 1:short preamble