rtmp_mac.h

ralink 2870 usb无线网卡 最新驱动

typedef	union	_CWMIN_CSR_STRUC	{
	struct	{
	    UINT32   Cwmin0:4;       // for AC_BE
	    UINT32   Cwmin1:4;       // for AC_BK
	    UINT32   Cwmin2:4;       // for AC_VI
	    UINT32   Cwmin3:4;       // for AC_VO
	    UINT32   Rsv:16;
	}	field;
	UINT32			word;
}	CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
#endif

//
// CWMAX_CSR: CWmin for each EDCA AC
//
#define WMM_CWMAX_CFG   0x021c
#ifdef RT_BIG_ENDIAN
typedef	union	_CWMAX_CSR_STRUC	{
	struct	{
	    UINT32   Rsv:16;
	    UINT32   Cwmax3:4;       // for AC_VO
	    UINT32   Cwmax2:4;       // for AC_VI
	    UINT32   Cwmax1:4;       // for AC_BK
	    UINT32   Cwmax0:4;       // for AC_BE
	}	field;
	UINT32			word;
}	CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
#else
typedef	union	_CWMAX_CSR_STRUC	{
	struct	{
	    UINT32   Cwmax0:4;       // for AC_BE
	    UINT32   Cwmax1:4;       // for AC_BK
	    UINT32   Cwmax2:4;       // for AC_VI
	    UINT32   Cwmax3:4;       // for AC_VO
	    UINT32   Rsv:16;
	}	field;
	UINT32			word;
}	CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
#endif


//
// AC_TXOP_CSR0: AC_BK/AC_BE TXOP register
//
#define WMM_TXOP0_CFG    0x0220
#ifdef RT_BIG_ENDIAN
typedef	union	_AC_TXOP_CSR0_STRUC	{
	struct	{
	    USHORT  Ac1Txop;        // for AC_BE, in unit of 32us
	    USHORT  Ac0Txop;        // for AC_BK, in unit of 32us
	}	field;
	UINT32			word;
}	AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
#else
typedef	union	_AC_TXOP_CSR0_STRUC	{
	struct	{
	    USHORT  Ac0Txop;        // for AC_BK, in unit of 32us
	    USHORT  Ac1Txop;        // for AC_BE, in unit of 32us
	}	field;
	UINT32			word;
}	AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
#endif

//
// AC_TXOP_CSR1: AC_VO/AC_VI TXOP register
//
#define WMM_TXOP1_CFG    0x0224
#ifdef RT_BIG_ENDIAN
typedef	union	_AC_TXOP_CSR1_STRUC	{
	struct	{
	    USHORT  Ac3Txop;        // for AC_VO, in unit of 32us
	    USHORT  Ac2Txop;        // for AC_VI, in unit of 32us
	}	field;
	UINT32			word;
}	AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
#else
typedef	union	_AC_TXOP_CSR1_STRUC	{
	struct	{
	    USHORT  Ac2Txop;        // for AC_VI, in unit of 32us
	    USHORT  Ac3Txop;        // for AC_VO, in unit of 32us
	}	field;
	UINT32			word;
}	AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
#endif


#define RINGREG_DIFF			0x10
#define GPIO_CTRL_CFG    0x0228	//MAC_CSR13
#define MCU_CMD_CFG    0x022c
#define TX_BASE_PTR0     0x0230	//AC_BK base address
#define TX_MAX_CNT0      0x0234
#define TX_CTX_IDX0       0x0238
#define TX_DTX_IDX0      0x023c
#define TX_BASE_PTR1     0x0240 	//AC_BE base address
#define TX_MAX_CNT1      0x0244
#define TX_CTX_IDX1       0x0248
#define TX_DTX_IDX1      0x024c
#define TX_BASE_PTR2     0x0250 	//AC_VI base address
#define TX_MAX_CNT2      0x0254
#define TX_CTX_IDX2       0x0258
#define TX_DTX_IDX2      0x025c
#define TX_BASE_PTR3     0x0260 	//AC_VO base address
#define TX_MAX_CNT3      0x0264
#define TX_CTX_IDX3       0x0268
#define TX_DTX_IDX3      0x026c
#define TX_BASE_PTR4     0x0270 	//HCCA base address
#define TX_MAX_CNT4      0x0274
#define TX_CTX_IDX4       0x0278
#define TX_DTX_IDX4      0x027c
#define TX_BASE_PTR5     0x0280 	//MGMT base address
#define  TX_MAX_CNT5     0x0284
#define TX_CTX_IDX5       0x0288
#define TX_DTX_IDX5      0x028c
#define TX_MGMTMAX_CNT      TX_MAX_CNT5
#define TX_MGMTCTX_IDX       TX_CTX_IDX5
#define TX_MGMTDTX_IDX      TX_DTX_IDX5
#define RX_BASE_PTR     0x0290 	//RX base address
#define RX_MAX_CNT      0x0294
#define RX_CRX_IDX       0x0298
#define RX_DRX_IDX      0x029c


#define USB_DMA_CFG      0x02a0
#ifdef RT_BIG_ENDIAN
typedef	union	_USB_DMA_CFG_STRUC	{
	struct	{
	    UINT32  TxBusy:1;   	//USB DMA TX FSM busy . debug only
	    UINT32  RxBusy:1;        //USB DMA RX FSM busy . debug only
	    UINT32  EpoutValid:6;        //OUT endpoint data valid. debug only
	    UINT32  TxBulkEn:1;        //Enable USB DMA Tx  
	    UINT32  RxBulkEn:1;        //Enable USB DMA Rx  
	    UINT32  RxBulkAggEn:1;        //Enable Rx Bulk Aggregation  
	    UINT32  TxopHalt:1;        //Halt TXOP count down when TX buffer is full.
	    UINT32  TxClear:1;        //Clear USB DMA TX path
	    UINT32  rsv:2;        
	    UINT32  phyclear:1;        		//phy watch dog enable. write 1
	    UINT32  RxBulkAggLmt:8;        //Rx Bulk Aggregation Limit  in unit of 1024 bytes
	    UINT32  RxBulkAggTOut:8;        //Rx Bulk Aggregation TimeOut  in unit of 33ns
	}	field;
	UINT32			word;
}	USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
#else
typedef	union	_USB_DMA_CFG_STRUC	{
	struct	{
	    UINT32  RxBulkAggTOut:8;        //Rx Bulk Aggregation TimeOut  in unit of 33ns
	    UINT32  RxBulkAggLmt:8;        //Rx Bulk Aggregation Limit  in unit of 256 bytes
	    UINT32  phyclear:1;        		//phy watch dog enable. write 1
	    UINT32  rsv:2;        
	    UINT32  TxClear:1;        //Clear USB DMA TX path
	    UINT32  TxopHalt:1;        //Halt TXOP count down when TX buffer is full.
	    UINT32  RxBulkAggEn:1;        //Enable Rx Bulk Aggregation  
	    UINT32  RxBulkEn:1;        //Enable USB DMA Rx  
	    UINT32  TxBulkEn:1;        //Enable USB DMA Tx  
	    UINT32  EpoutValid:6;        //OUT endpoint data valid
	    UINT32  RxBusy:1;        //USB DMA RX FSM busy 
	    UINT32  TxBusy:1;   	//USB DMA TX FSM busy 
	}	field;
	UINT32			word;
}	USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
#endif


//
//  3  PBF  registers  
//
//
// Most are for debug. Driver doesn't touch PBF register.
#define PBF_SYS_CTRL 	 0x0400
#define PBF_CFG                 0x0408
#define PBF_MAX_PCNT 	 0x040C
#define PBF_CTRL	 	0x0410
#define PBF_INT_STA	 0x0414
#define PBF_INT_ENA	 0x0418
#define TXRXQ_PCNT  	 0x0438
#define PBF_DBG 	 	 0x043c
#define PBF_CAP_CTRL     0x0440


#define LDO_CFG0 				0x05d4
#define GPIO_SWITCH				0x05dc


//
//  4  MAC  registers  
//
//
//  4.1 MAC SYSTEM  configuration registers (offset:0x1000)
//
#define MAC_CSR0            0x1000
#ifdef RT_BIG_ENDIAN
typedef	union	_ASIC_VER_ID_STRUC	{
	struct	{
	    USHORT  ASICVer;        // version : 2860
	    USHORT  ASICRev;        // reversion  : 0
	}	field;
	UINT32			word;
}	ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
#else
typedef	union	_ASIC_VER_ID_STRUC	{
	struct	{
	    USHORT  ASICRev;        // reversion  : 0
	    USHORT  ASICVer;        // version : 2860
	}	field;
	UINT32			word;
}	ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
#endif
#define MAC_SYS_CTRL            0x1004		//MAC_CSR1
#define MAC_ADDR_DW0            		0x1008		// MAC ADDR DW0
#define MAC_ADDR_DW1           		 0x100c		// MAC ADDR DW1
//
// MAC_CSR2: STA MAC register 0
//
#ifdef RT_BIG_ENDIAN
typedef	union	_MAC_DW0_STRUC	{
	struct	{
		UCHAR		Byte3;		// MAC address byte 3
		UCHAR		Byte2;		// MAC address byte 2
		UCHAR		Byte1;		// MAC address byte 1
		UCHAR		Byte0;		// MAC address byte 0
	}	field;
	UINT32			word;
}	MAC_DW0_STRUC, *PMAC_DW0_STRUC;
#else
typedef	union	_MAC_DW0_STRUC	{
	struct	{
		UCHAR		Byte0;		// MAC address byte 0
		UCHAR		Byte1;		// MAC address byte 1
		UCHAR		Byte2;		// MAC address byte 2
		UCHAR		Byte3;		// MAC address byte 3
	}	field;
	UINT32			word;
}	MAC_DW0_STRUC, *PMAC_DW0_STRUC;
#endif

//
// MAC_CSR3: STA MAC register 1
//
#ifdef RT_BIG_ENDIAN
typedef	union	_MAC_DW1_STRUC	{
	struct	{
		UCHAR		Rsvd1;
		UCHAR		U2MeMask;
		UCHAR		Byte5;		// MAC address byte 5
		UCHAR		Byte4;		// MAC address byte 4
	}	field;
	UINT32			word;
}	MAC_DW1_STRUC, *PMAC_DW1_STRUC;
#else
typedef	union	_MAC_DW1_STRUC	{
	struct	{
		UCHAR		Byte4;		// MAC address byte 4
		UCHAR		Byte5;		// MAC address byte 5
		UCHAR		U2MeMask;
		UCHAR		Rsvd1;
	}	field;
	UINT32			word;
}	MAC_DW1_STRUC, *PMAC_DW1_STRUC;
#endif

#define MAC_BSSID_DW0            		0x1010		// MAC BSSID DW0
#define MAC_BSSID_DW1            		0x1014		// MAC BSSID DW1

//
// MAC_CSR5: BSSID register 1
//
#ifdef RT_BIG_ENDIAN
typedef	union	_MAC_CSR5_STRUC	{
	struct	{
		USHORT		Rsvd:11;
		USHORT		MBssBcnNum:3;
		USHORT		BssIdMode:2; // 0: one BSSID, 10: 4 BSSID,  01: 2 BSSID , 11: 8BSSID
		UCHAR		Byte5;		 // BSSID byte 5
		UCHAR		Byte4;		 // BSSID byte 4
	}	field;
	UINT32			word;
}	MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
#else
typedef	union	_MAC_CSR5_STRUC	{
	struct	{
		UCHAR		Byte4;		 // BSSID byte 4
		UCHAR		Byte5;		 // BSSID byte 5
		USHORT      	BssIdMask:2; // 0: one BSSID, 10: 4 BSSID,  01: 2 BSSID , 11: 8BSSID
		USHORT		MBssBcnNum:3;
		USHORT		Rsvd:11;
	}	field;
	UINT32			word;
}	MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
#endif

#define MAX_LEN_CFG              0x1018		// rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
#define BBP_CSR_CFG            		0x101c		//  
//
// BBP_CSR_CFG: BBP serial control register
//
#ifdef RT_BIG_ENDIAN
typedef	union	_BBP_CSR_CFG_STRUC	{
	struct	{
		UINT32		:12;		
		UINT32		BBP_RW_MODE:1;		// 0: use serial mode  1:parallel
		UINT32		BBP_PAR_DUR:1;		    // 0: 4 MAC clock cycles  1: 8 MAC clock cycles
		UINT32		Busy:1;				// 1: ASIC is busy execute BBP programming.	
		UINT32		fRead:1;		    // 0: Write	BBP, 1:	Read BBP
		UINT32		RegNum:8;			// Selected	BBP	register
		UINT32		Value:8;			// Register	value to program into BBP
	}	field;
	UINT32			word;
}	BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
#else
typedef	union	_BBP_CSR_CFG_STRUC	{
	struct	{
		UINT32		Value:8;			// Register	value to program into BBP
		UINT32		RegNum:8;			// Selected	BBP	register
		UINT32		fRead:1;		    // 0: Write	BBP, 1:	Read BBP
		UINT32		Busy:1;				// 1: ASIC is busy execute BBP programming.	
		UINT32		BBP_PAR_DUR:1;		     // 0: 4 MAC clock cycles  1: 8 MAC clock cycles
		UINT32		BBP_RW_MODE:1;		// 0: use serial mode  1:parallel
		UINT32		:12;
	}	field;
	UINT32			word;
}	BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
#endif
#define RF_CSR_CFG0            		0x1020		 
//
// RF_CSR_CFG: RF control register
//
#ifdef RT_BIG_ENDIAN
typedef	union	_RF_CSR_CFG0_STRUC	{
	struct	{
		UINT32		Busy:1;		    // 0: idle 1: 8busy
		UINT32		Sel:1;				// 0:RF_LE0 activate  1:RF_LE1 activate	
		UINT32		StandbyMode:1;		    // 0: high when stand by 1:	low when standby
		UINT32		bitwidth:5;			// Selected	BBP	register
		UINT32		RegIdAndContent:24;			// Register	value to program into BBP
	}	field;
	UINT32			word;
}	RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
#else
typedef	union	_RF_CSR_CFG0_STRUC	{
	struct	{
		UINT32		RegIdAndContent:24;			// Register	value to program into BBP
		UINT32		bitwidth:5;			// Selected	BBP	register
		UINT32		StandbyMode:1;		    // 0: high when stand by 1:	low when standby
		UINT32		Sel:1;				// 0:RF_LE0 activate  1:RF_LE1 activate	
		UINT32		Busy:1;		    // 0: idle 1: 8busy
	}	field;
	UINT32			word;
}	RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
#endif
#define RF_CSR_CFG1           		0x1024		 
#ifdef RT_BIG_ENDIAN
typedef	union	_RF_CSR_CFG1_STRUC	{
	struct	{
		UINT32		rsv:7;		    // 0: idle 1: 8busy
		UINT32		RFGap:5;			// Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
		UINT32		RegIdAndContent:24;			// Register	value to program into BBP
	}	field;
	UINT32			word;
}	RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
#else
typedef	union	_RF_CSR_CFG1_STRUC	{
	struct	{
		UINT32		RegIdAndContent:24;			// Register	value to program into BBP
		UINT32		RFGap:5;			// Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
		UINT32		rsv:7;		    // 0: idle 1: 8busy
	}	field;
	UINT32			word;
}	RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
#endif
#define RF_CSR_CFG2           		0x1028		//  
#ifdef RT_BIG_ENDIAN
typedef	union	_RF_CSR_CFG2_STRUC	{
	struct	{
		UINT32		rsv:8;		    // 0: idle 1: 8busy
		UINT32		RegIdAndContent:24;			// Register	value to program into BBP
	}	field;
	UINT32			word;
}	RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
#else
typedef	union	_RF_CSR_CFG2_STRUC	{
	struct	{
		UINT32		RegIdAndContent:24;			// Register	value to program into BBP
		UINT32		rsv:8;		    // 0: idle 1: 8busy
	}	field;
	UINT32			word;
}	RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
#endif
#define LED_CFG           		0x102c		//  MAC_CSR14
#ifdef RT_BIG_ENDIAN
typedef	union	_LED_CFG_STRUC	{
	struct	{
		UINT32		:1;			 
		UINT32		LedPolar:1;			// Led Polarity.  0: active low1: active high
		UINT32		YLedMode:2;			// yellow Led Mode
		UINT32		GLedMode:2;			// green Led Mode
		UINT32		RLedMode:2;			// red Led Mode    0: off1: blinking upon TX2: periodic slow blinking3: always on
		UINT32		rsv:2;		    
		UINT32		SlowBlinkPeriod:6;			// slow blinking period. unit:1ms
		UINT32		OffPeriod:8;			// blinking off period unit 1ms
		UINT32		OnPeriod:8;			// blinking on period unit 1ms
	}	field;
	UINT32			word;
}	LED_CFG_STRUC, *PLED_CFG_STRUC;
#else
typedef	union	_LED_CFG_STRUC	{
	struct	{
		UINT32		OnPeriod:8;			// blinking on period unit 1ms
		UINT32		OffPeriod:8;			// blinking off period unit 1ms
		UINT32		SlowBlinkPeriod:6;			// slow blinking period. unit:1ms
		UINT32		rsv:2;		    
		UINT32		RLedMode:2;			// red Led Mode    0: off1: blinking upon TX2: periodic slow blinking3: always on
		UINT32		GLedMode:2;			// green Led Mode
		UINT32		YLedMode:2;			// yellow Led Mode
		UINT32		LedPolar:1;			// Led Polarity.  0: active low1: active high
		UINT32		:1;			 
	}	field;
	UINT32			word;
}	LED_CFG_STRUC, *PLED_CFG_STRUC;
#endif
//
//  4.2 MAC TIMING  configuration registers (offset:0x1100)
//
#define XIFS_TIME_CFG             0x1100		 // MAC_CSR8  MAC_CSR9   
#ifdef RT_BIG_ENDIAN
typedef	union	_IFS_SLOT_CFG_STRUC	{
	struct	{
	    UINT32  rsv:2;         
	    UINT32  BBRxendEnable:1;        //  reference RXEND signal to begin XIFS defer
	    UINT32  EIFS:9;        //  unit 1us
	    UINT32  OfdmXifsTime:4;        //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
	    UINT32  OfdmSifsTime:8;        //  unit 1us. Applied after OFDM RX/TX
	    UINT32  CckmSifsTime:8;        //  unit 1us. Applied after CCK RX/TX
	}	field;
	UINT32			word;
}	IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
#else
typedef	union	_IFS_SLOT_CFG_STRUC	{
	struct	{