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-- Node name is '|CD:11|:28' = '|CD:11|q9'
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = DFFE( _EQ012, clk, VCC, VCC, VCC);
_EQ012 = _LC4_C6 & !_LC6_D11
# _LC1_F1 & _LC6_D11;
-- Node name is '|CD:11|:27' = '|CD:11|q10'
-- Equation name is '_LC1_F1', type is buried
_LC1_F1 = DFFE( _EQ013, clk, VCC, VCC, VCC);
_EQ013 = _LC3_F1 & !_LC6_D11
# _LC6_D11 & _LC7_F1;
-- Node name is '|CD:11|:26' = '|CD:11|q11'
-- Equation name is '_LC7_F1', type is buried
_LC7_F1 = DFFE( _EQ014, clk, VCC, VCC, VCC);
_EQ014 = _LC5_F1 & !_LC6_D11
# _LC4_F1 & _LC6_D11;
-- Node name is '|CD:11|:25' = '|CD:11|q12'
-- Equation name is '_LC4_F1', type is buried
_LC4_F1 = DFFE( _EQ015, clk, VCC, VCC, VCC);
_EQ015 = !_LC6_D11 & _LC6_F1
# _LC2_F1 & _LC6_D11;
-- Node name is '|CD:11|:24' = '|CD:11|q13'
-- Equation name is '_LC2_F1', type is buried
_LC2_F1 = DFFE( _EQ016, clk, VCC, VCC, VCC);
_EQ016 = !_LC6_D11 & _LC8_F1
# _LC1_D11 & _LC6_D11;
-- Node name is '|CD:11|:23' = '|CD:11|q14'
-- Equation name is '_LC1_D11', type is buried
_LC1_D11 = DFFE( _EQ017, clk, VCC, VCC, VCC);
_EQ017 = _LC1_F4 & !_LC6_D11
# _LC6_D11 & _LC8_D11;
-- Node name is '|CD:11|:22' = '|CD:11|q15'
-- Equation name is '_LC8_D11', type is buried
_LC8_D11 = DFFE( _EQ018, clk, VCC, VCC, VCC);
_EQ018 = _LC5_D11
# _LC7_D11 & _LC8_D11
# _LC6_D11;
-- Node name is '|CD:11|:111'
-- Equation name is '_LC6_D11', type is buried
_LC6_D11 = LCELL( _EQ019);
_EQ019 = !_LC2_D11 & !_LC4_D11 & !_LC7_D6;
-- Node name is '|CD:11|:115'
-- Equation name is '_LC3_D11', type is buried
!_LC3_D11 = _LC3_D11~NOT;
_LC3_D11~NOT = LCELL( _EQ020);
_EQ020 = _LC4_D11
# _LC2_D11
# !_LC7_D6;
-- Node name is '|CD:11|~491~1'
-- Equation name is '_LC1_D6', type is buried
-- synthesized logic cell
_LC1_D6 = LCELL( _EQ021);
_EQ021 = _LC8_D6
# _LC6_D6
# _LC8_D4;
-- Node name is '|CD:11|:491'
-- Equation name is '_LC4_D6', type is buried
!_LC4_D6 = _LC4_D6~NOT;
_LC4_D6~NOT = LCELL( _EQ022);
_EQ022 = _LC1_D11
# _LC3_D6
# _LC1_D6;
-- Node name is '|CD:11|:580'
-- Equation name is '_LC5_D11', type is buried
_LC5_D11 = LCELL( _EQ023);
_EQ023 = _LC1_D11 & !_LC2_D11 & !_LC4_D11 & _LC7_D6;
-- Node name is '|CD:11|~581~1'
-- Equation name is '_LC7_D11', type is buried
-- synthesized logic cell
_LC7_D11 = LCELL( _EQ024);
_EQ024 = _LC2_D11
# _LC4_D11 & _LC7_D6
# !_LC4_D11 & !_LC7_D6;
-- Node name is '|CD:11|:594'
-- Equation name is '_LC1_F4', type is buried
_LC1_F4 = LCELL( _EQ025);
_EQ025 = _LC1_D11 & _LC7_D11
# _LC2_F1 & _LC3_D11;
-- Node name is '|CD:11|:606'
-- Equation name is '_LC8_F1', type is buried
_LC8_F1 = LCELL( _EQ026);
_EQ026 = _LC2_F1 & _LC7_D11
# _LC3_D11 & _LC4_F1;
-- Node name is '|CD:11|:618'
-- Equation name is '_LC6_F1', type is buried
_LC6_F1 = LCELL( _EQ027);
_EQ027 = _LC4_F1 & _LC7_D11
# _LC3_D11 & _LC7_F1;
-- Node name is '|CD:11|:630'
-- Equation name is '_LC5_F1', type is buried
_LC5_F1 = LCELL( _EQ028);
_EQ028 = _LC7_D11 & _LC7_F1
# _LC1_F1 & _LC3_D11;
-- Node name is '|CD:11|:642'
-- Equation name is '_LC3_F1', type is buried
_LC3_F1 = LCELL( _EQ029);
_EQ029 = _LC1_F1 & _LC7_D11
# _LC1_C3 & _LC3_D11;
-- Node name is '|CD:11|:654'
-- Equation name is '_LC4_C6', type is buried
_LC4_C6 = LCELL( _EQ030);
_EQ030 = _LC1_C3 & _LC7_D11
# _LC1_C6 & _LC3_D11;
-- Node name is '|CD:11|:666'
-- Equation name is '_LC5_C6', type is buried
_LC5_C6 = LCELL( _EQ031);
_EQ031 = _LC1_C6 & _LC7_D11
# _LC2_C6 & _LC3_D11;
-- Node name is '|CD:11|:678'
-- Equation name is '_LC3_C6', type is buried
_LC3_C6 = LCELL( _EQ032);
_EQ032 = _LC2_C6 & _LC7_D11
# _LC1_D7 & _LC3_D11;
-- Node name is '|CD:11|:690'
-- Equation name is '_LC8_D9', type is buried
_LC8_D9 = LCELL( _EQ033);
_EQ033 = _LC1_D7 & _LC7_D11
# _LC3_D11 & _LC4_D7;
-- Node name is '|CD:11|:702'
-- Equation name is '_LC1_D9', type is buried
_LC1_D9 = LCELL( _EQ034);
_EQ034 = _LC4_D7 & _LC7_D11
# _LC2_D9 & _LC3_D11;
-- Node name is '|CD:11|:714'
-- Equation name is '_LC7_D9', type is buried
_LC7_D9 = LCELL( _EQ035);
_EQ035 = _LC2_D9 & _LC7_D11
# _LC3_D9 & _LC3_D11;
-- Node name is '|CD:11|:726'
-- Equation name is '_LC5_D9', type is buried
_LC5_D9 = LCELL( _EQ036);
_EQ036 = _LC3_D9 & _LC7_D11
# _LC3_D11 & _LC6_D9;
-- Node name is '|CD:11|:738'
-- Equation name is '_LC4_D9', type is buried
_LC4_D9 = LCELL( _EQ037);
_EQ037 = _LC6_D9 & _LC7_D11
# _LC3_D11 & _LC4_C12;
-- Node name is '|CD:11|:750'
-- Equation name is '_LC2_C12', type is buried
_LC2_C12 = LCELL( _EQ038);
_EQ038 = _LC4_C12 & _LC7_D11
# _LC1_C12 & _LC3_D11;
-- Node name is '|CD:11|:798'
-- Equation name is '_LC2_D6', type is buried
_LC2_D6 = LCELL( _EQ039);
_EQ039 = _LC3_D11 & !_LC4_D6
# !_LC3_D11 & _LC7_D6;
-- Node name is '|COUNT_16:2|:9' = '|COUNT_16:2|AL0'
-- Equation name is '_LC3_D6', type is buried
_LC3_D6 = DFFE(!_LC3_D6, disclk, VCC, VCC, VCC);
-- Node name is '|COUNT_16:2|:8' = '|COUNT_16:2|AL1'
-- Equation name is '_LC8_D4', type is buried
_LC8_D4 = DFFE( _EQ040, disclk, VCC, VCC, VCC);
_EQ040 = !_LC3_D6 & _LC8_D4
# _LC3_D6 & !_LC8_D4;
-- Node name is '|COUNT_16:2|:7' = '|COUNT_16:2|AL2'
-- Equation name is '_LC6_D6', type is buried
_LC6_D6 = DFFE( _EQ041, disclk, VCC, VCC, VCC);
_EQ041 = _LC6_D6 & !_LC8_D4
# !_LC3_D6 & _LC6_D6
# _LC3_D6 & !_LC6_D6 & _LC8_D4;
-- Node name is '|COUNT_16:2|:6' = '|COUNT_16:2|AL3'
-- Equation name is '_LC8_D6', type is buried
_LC8_D6 = DFFE( _EQ042, disclk, VCC, VCC, VCC);
_EQ042 = !_LC8_D4 & _LC8_D6
# !_LC3_D6 & _LC8_D6
# !_LC6_D6 & _LC8_D6
# _LC3_D6 & _LC6_D6 & _LC8_D4 & !_LC8_D6;
-- Node name is '|COUNT_16:2|:27'
-- Equation name is '_LC5_D6', type is buried
_LC5_D6 = LCELL( _EQ043);
_EQ043 = _LC3_D6 & _LC6_D6 & _LC8_D4 & _LC8_D6;
Project Information d:\k5\top.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 39,170K
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