📄 top.rpt
字号:
80 - - F -- OUTPUT 0 1 0 0 qq13
81 - - F -- OUTPUT 0 1 0 0 qq14
82 - - E -- OUTPUT 0 1 0 0 qq15
20 - - D -- OUTPUT 0 1 0 0 s0
21 - - D -- OUTPUT 0 1 0 0 s1
22 - - D -- OUTPUT 0 1 0 0 s2
28 - - E -- OUTPUT 0 1 0 0 s3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\k5\top.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - D 11 DFFE 1 3 1 1 |CD:11|q15 (|CD:11|:22)
- 1 - D 11 DFFE 1 3 1 4 |CD:11|q14 (|CD:11|:23)
- 2 - F 01 DFFE 1 3 1 3 |CD:11|q13 (|CD:11|:24)
- 4 - F 01 DFFE 1 3 1 3 |CD:11|q12 (|CD:11|:25)
- 7 - F 01 DFFE 1 3 1 3 |CD:11|q11 (|CD:11|:26)
- 1 - F 01 DFFE 1 3 1 3 |CD:11|q10 (|CD:11|:27)
- 1 - C 03 DFFE 1 3 1 3 |CD:11|q9 (|CD:11|:28)
- 1 - C 06 DFFE 1 3 1 3 |CD:11|q8 (|CD:11|:29)
- 2 - C 06 DFFE 1 3 1 3 |CD:11|q7 (|CD:11|:30)
- 1 - D 07 DFFE 1 3 1 3 |CD:11|q6 (|CD:11|:31)
- 4 - D 07 DFFE 1 3 1 3 |CD:11|q5 (|CD:11|:32)
- 2 - D 09 DFFE 1 3 1 3 |CD:11|q4 (|CD:11|:33)
- 3 - D 09 DFFE 1 3 1 3 |CD:11|q3 (|CD:11|:34)
- 6 - D 09 DFFE 1 3 1 3 |CD:11|q2 (|CD:11|:35)
- 4 - C 12 DFFE 1 3 1 4 |CD:11|q1 (|CD:11|:36)
- 1 - C 12 DFFE 1 3 1 1 |CD:11|q0 (|CD:11|:37)
- 2 - D 11 DFFE 1 0 0 5 |CD:11|flag2 (|CD:11|:38)
- 4 - D 11 DFFE 1 3 0 4 |CD:11|flag1 (|CD:11|:39)
- 7 - D 06 DFFE 1 4 0 6 |CD:11|flag0 (|CD:11|:40)
- 6 - D 11 AND2 0 3 0 17 |CD:11|:111
- 3 - D 11 OR2 ! 0 3 0 15 |CD:11|:115
- 1 - D 06 OR2 s 0 3 0 1 |CD:11|~491~1
- 4 - D 06 OR2 ! 0 3 0 2 |CD:11|:491
- 5 - D 11 AND2 0 4 0 1 |CD:11|:580
- 7 - D 11 OR2 s 0 3 0 16 |CD:11|~581~1
- 1 - F 04 OR2 0 4 0 1 |CD:11|:594
- 8 - F 01 OR2 0 4 0 1 |CD:11|:606
- 6 - F 01 OR2 0 4 0 1 |CD:11|:618
- 5 - F 01 OR2 0 4 0 1 |CD:11|:630
- 3 - F 01 OR2 0 4 0 1 |CD:11|:642
- 4 - C 06 OR2 0 4 0 1 |CD:11|:654
- 5 - C 06 OR2 0 4 0 1 |CD:11|:666
- 3 - C 06 OR2 0 4 0 1 |CD:11|:678
- 8 - D 09 OR2 0 4 0 1 |CD:11|:690
- 1 - D 09 OR2 0 4 0 1 |CD:11|:702
- 7 - D 09 OR2 0 4 0 1 |CD:11|:714
- 5 - D 09 OR2 0 4 0 1 |CD:11|:726
- 4 - D 09 OR2 0 4 0 1 |CD:11|:738
- 2 - C 12 OR2 0 4 0 1 |CD:11|:750
- 2 - D 06 OR2 0 3 0 1 |CD:11|:798
- 8 - D 06 DFFE 1 3 1 2 |COUNT_16:2|AL3 (|COUNT_16:2|:6)
- 6 - D 06 DFFE 1 2 1 3 |COUNT_16:2|AL2 (|COUNT_16:2|:7)
- 8 - D 04 DFFE 1 1 1 4 |COUNT_16:2|AL1 (|COUNT_16:2|:8)
- 3 - D 06 DFFE 1 0 1 5 |COUNT_16:2|AL0 (|COUNT_16:2|:9)
- 5 - D 06 AND2 0 4 0 1 |COUNT_16:2|:27
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\k5\top.rpt
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** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 2/ 96( 2%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 7/ 96( 7%) 12/ 48( 25%) 0/ 48( 0%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
E: 2/ 96( 2%) 1/ 48( 2%) 0/ 48( 0%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
F: 0/ 96( 0%) 10/ 48( 20%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 6/24( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\k5\top.rpt
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** CLOCK SIGNALS **
Type Fan-out Name
INPUT 19 clk
INPUT 4 disclk
Device-Specific Information: d:\k5\top.rpt
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** EQUATIONS **
clk : INPUT;
disclk : INPUT;
-- Node name is 'qq0'
-- Equation name is 'qq0', type is output
qq0 = _LC1_C12;
-- Node name is 'qq1'
-- Equation name is 'qq1', type is output
qq1 = _LC4_C12;
-- Node name is 'qq2'
-- Equation name is 'qq2', type is output
qq2 = _LC6_D9;
-- Node name is 'qq3'
-- Equation name is 'qq3', type is output
qq3 = _LC3_D9;
-- Node name is 'qq4'
-- Equation name is 'qq4', type is output
qq4 = _LC2_D9;
-- Node name is 'qq5'
-- Equation name is 'qq5', type is output
qq5 = _LC4_D7;
-- Node name is 'qq6'
-- Equation name is 'qq6', type is output
qq6 = _LC1_D7;
-- Node name is 'qq7'
-- Equation name is 'qq7', type is output
qq7 = _LC2_C6;
-- Node name is 'qq8'
-- Equation name is 'qq8', type is output
qq8 = _LC1_C6;
-- Node name is 'qq9'
-- Equation name is 'qq9', type is output
qq9 = _LC1_C3;
-- Node name is 'qq10'
-- Equation name is 'qq10', type is output
qq10 = _LC1_F1;
-- Node name is 'qq11'
-- Equation name is 'qq11', type is output
qq11 = _LC7_F1;
-- Node name is 'qq12'
-- Equation name is 'qq12', type is output
qq12 = _LC4_F1;
-- Node name is 'qq13'
-- Equation name is 'qq13', type is output
qq13 = _LC2_F1;
-- Node name is 'qq14'
-- Equation name is 'qq14', type is output
qq14 = _LC1_D11;
-- Node name is 'qq15'
-- Equation name is 'qq15', type is output
qq15 = _LC8_D11;
-- Node name is 's0'
-- Equation name is 's0', type is output
s0 = _LC3_D6;
-- Node name is 's1'
-- Equation name is 's1', type is output
s1 = _LC8_D4;
-- Node name is 's2'
-- Equation name is 's2', type is output
s2 = _LC6_D6;
-- Node name is 's3'
-- Equation name is 's3', type is output
s3 = _LC8_D6;
-- Node name is '|CD:11|:40' = '|CD:11|flag0'
-- Equation name is '_LC7_D6', type is buried
_LC7_D6 = DFFE( _EQ001, clk, VCC, VCC, VCC);
_EQ001 = _LC2_D6 & !_LC6_D11
# _LC4_C12 & _LC5_D6 & _LC6_D11;
-- Node name is '|CD:11|:39' = '|CD:11|flag1'
-- Equation name is '_LC4_D11', type is buried
_LC4_D11 = DFFE( _EQ002, clk, VCC, VCC, VCC);
_EQ002 = !_LC2_D11 & _LC4_D6 & _LC7_D6
# _LC2_D11 & _LC4_D11
# _LC4_D11 & _LC7_D6;
-- Node name is '|CD:11|:38' = '|CD:11|flag2'
-- Equation name is '_LC2_D11', type is buried
_LC2_D11 = DFFE( _LC2_D11, clk, VCC, VCC, VCC);
-- Node name is '|CD:11|:37' = '|CD:11|q0'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = DFFE( _EQ003, clk, VCC, VCC, VCC);
_EQ003 = _LC4_C12 & _LC6_D11
# _LC1_C12 & !_LC6_D11 & _LC7_D11;
-- Node name is '|CD:11|:36' = '|CD:11|q1'
-- Equation name is '_LC4_C12', type is buried
_LC4_C12 = DFFE( _EQ004, clk, VCC, VCC, VCC);
_EQ004 = _LC2_C12 & !_LC6_D11
# _LC6_D9 & _LC6_D11;
-- Node name is '|CD:11|:35' = '|CD:11|q2'
-- Equation name is '_LC6_D9', type is buried
_LC6_D9 = DFFE( _EQ005, clk, VCC, VCC, VCC);
_EQ005 = _LC4_D9 & !_LC6_D11
# _LC3_D9 & _LC6_D11;
-- Node name is '|CD:11|:34' = '|CD:11|q3'
-- Equation name is '_LC3_D9', type is buried
_LC3_D9 = DFFE( _EQ006, clk, VCC, VCC, VCC);
_EQ006 = _LC5_D9 & !_LC6_D11
# _LC2_D9 & _LC6_D11;
-- Node name is '|CD:11|:33' = '|CD:11|q4'
-- Equation name is '_LC2_D9', type is buried
_LC2_D9 = DFFE( _EQ007, clk, VCC, VCC, VCC);
_EQ007 = !_LC6_D11 & _LC7_D9
# _LC4_D7 & _LC6_D11;
-- Node name is '|CD:11|:32' = '|CD:11|q5'
-- Equation name is '_LC4_D7', type is buried
_LC4_D7 = DFFE( _EQ008, clk, VCC, VCC, VCC);
_EQ008 = _LC1_D9 & !_LC6_D11
# _LC1_D7 & _LC6_D11;
-- Node name is '|CD:11|:31' = '|CD:11|q6'
-- Equation name is '_LC1_D7', type is buried
_LC1_D7 = DFFE( _EQ009, clk, VCC, VCC, VCC);
_EQ009 = !_LC6_D11 & _LC8_D9
# _LC2_C6 & _LC6_D11;
-- Node name is '|CD:11|:30' = '|CD:11|q7'
-- Equation name is '_LC2_C6', type is buried
_LC2_C6 = DFFE( _EQ010, clk, VCC, VCC, VCC);
_EQ010 = _LC3_C6 & !_LC6_D11
# _LC1_C6 & _LC6_D11;
-- Node name is '|CD:11|:29' = '|CD:11|q8'
-- Equation name is '_LC1_C6', type is buried
_LC1_C6 = DFFE( _EQ011, clk, VCC, VCC, VCC);
_EQ011 = _LC5_C6 & !_LC6_D11
# _LC1_C3 & _LC6_D11;
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