📄 cd_1.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\k\cd_1.rpt
cd_1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - E 20 DFFE + 0 3 1 1 q15 (:22)
- 1 - E 20 DFFE + 0 3 1 3 q14 (:23)
- 5 - E 20 DFFE + 0 3 1 3 q13 (:24)
- 2 - E 20 DFFE + 0 3 1 3 q12 (:25)
- 6 - C 22 DFFE + 0 3 1 3 q11 (:26)
- 4 - C 22 DFFE + 0 3 1 3 q10 (:27)
- 1 - C 22 DFFE + 0 3 1 3 q9 (:28)
- 8 - C 22 DFFE + 0 3 1 1 q8 (:29)
- 2 - A 15 DFFE + 0 3 1 1 q7 (:30)
- 7 - A 15 DFFE + 0 3 1 4 q6 (:31)
- 1 - A 15 DFFE + 0 3 1 3 q5 (:32)
- 2 - A 22 DFFE + 0 3 1 3 q4 (:33)
- 8 - A 22 DFFE + 0 3 1 3 q3 (:34)
- 3 - A 22 DFFE + 0 3 1 3 q2 (:35)
- 6 - A 22 DFFE + 0 3 1 4 q1 (:36)
- 4 - E 20 DFFE + 0 3 1 1 q0 (:37)
- 6 - A 17 DFFE + 0 0 0 4 flag2 (:38)
- 7 - A 17 DFFE + 0 3 0 3 flag1 (:39)
- 5 - A 17 DFFE + 0 4 0 5 flag0 (:40)
- 2 - A 17 AND2 0 3 0 17 :143
- 4 - A 17 OR2 ! 0 3 0 15 :147
- 5 - A 15 OR2 ! 1 2 0 2 :871
- 7 - E 20 OR2 0 4 0 1 :974
- 1 - A 17 OR2 s 0 3 0 16 ~976~1
- 6 - E 20 OR2 0 4 0 1 :986
- 3 - E 20 OR2 0 4 0 1 :998
- 7 - C 22 OR2 0 4 0 1 :1010
- 5 - C 22 OR2 0 4 0 1 :1022
- 3 - C 22 OR2 0 4 0 1 :1034
- 2 - C 22 AND2 0 2 0 1 :1047
- 8 - A 15 AND2 0 2 0 1 :1059
- 6 - A 15 OR2 0 4 0 1 :1070
- 4 - A 15 OR2 0 4 0 1 :1082
- 7 - A 22 OR2 0 4 0 1 :1094
- 5 - A 22 OR2 0 4 0 1 :1106
- 4 - A 22 OR2 0 4 0 1 :1118
- 1 - A 22 OR2 0 4 0 1 :1130
- 3 - A 17 OR2 0 3 0 1 :1178
- 1 - A 19 AND2 s 3 0 0 2 ~1182~1
- 3 - A 15 AND2 s 1 1 0 1 ~1182~2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\k\cd_1.rpt
cd_1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 0/ 48( 0%) 10/ 48( 20%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/ 96( 1%) 0/ 48( 0%) 6/ 48( 12%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 3/ 96( 3%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\k\cd_1.rpt
cd_1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 19 clk
Device-Specific Information: d:\k\cd_1.rpt
cd_1
** EQUATIONS **
ah0 : INPUT;
ah1 : INPUT;
ah2 : INPUT;
ah3 : INPUT;
clk : INPUT;
-- Node name is ':40' = 'flag0'
-- Equation name is 'flag0', location is LC5_A17, type is buried.
flag0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC2_A17 & _LC3_A17
# _LC2_A17 & _LC3_A15 & q1;
-- Node name is ':39' = 'flag1'
-- Equation name is 'flag1', location is LC7_A17, type is buried.
flag1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = flag0 & !flag2 & _LC5_A15
# flag1 & flag2
# flag0 & flag1;
-- Node name is ':38' = 'flag2'
-- Equation name is 'flag2', location is LC6_A17, type is buried.
flag2 = DFFE( flag2, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'qq0'
-- Equation name is 'qq0', type is output
qq0 = q0;
-- Node name is 'qq1'
-- Equation name is 'qq1', type is output
qq1 = q1;
-- Node name is 'qq2'
-- Equation name is 'qq2', type is output
qq2 = q2;
-- Node name is 'qq3'
-- Equation name is 'qq3', type is output
qq3 = q3;
-- Node name is 'qq4'
-- Equation name is 'qq4', type is output
qq4 = q4;
-- Node name is 'qq5'
-- Equation name is 'qq5', type is output
qq5 = q5;
-- Node name is 'qq6'
-- Equation name is 'qq6', type is output
qq6 = q6;
-- Node name is 'qq7'
-- Equation name is 'qq7', type is output
qq7 = q7;
-- Node name is 'qq8'
-- Equation name is 'qq8', type is output
qq8 = q8;
-- Node name is 'qq9'
-- Equation name is 'qq9', type is output
qq9 = q9;
-- Node name is 'qq10'
-- Equation name is 'qq10', type is output
qq10 = q10;
-- Node name is 'qq11'
-- Equation name is 'qq11', type is output
qq11 = q11;
-- Node name is 'qq12'
-- Equation name is 'qq12', type is output
qq12 = q12;
-- Node name is 'qq13'
-- Equation name is 'qq13', type is output
qq13 = q13;
-- Node name is 'qq14'
-- Equation name is 'qq14', type is output
qq14 = q14;
-- Node name is 'qq15'
-- Equation name is 'qq15', type is output
qq15 = q15;
-- Node name is ':37' = 'q0'
-- Equation name is 'q0', location is LC4_E20, type is buried.
q0 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC2_A17 & q1
# _LC1_A17 & !_LC2_A17 & q0;
-- Node name is ':36' = 'q1'
-- Equation name is 'q1', location is LC6_A22, type is buried.
q1 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC1_A22 & !_LC2_A17
# _LC2_A17 & q2;
-- Node name is ':35' = 'q2'
-- Equation name is 'q2', location is LC3_A22, type is buried.
q2 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC2_A17 & _LC4_A22
# _LC2_A17 & q3;
-- Node name is ':34' = 'q3'
-- Equation name is 'q3', location is LC8_A22, type is buried.
q3 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !_LC2_A17 & _LC5_A22
# _LC2_A17 & q4;
-- Node name is ':33' = 'q4'
-- Equation name is 'q4', location is LC2_A22, type is buried.
q4 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !_LC2_A17 & _LC7_A22
# _LC2_A17 & q5;
-- Node name is ':32' = 'q5'
-- Equation name is 'q5', location is LC1_A15, type is buried.
q5 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !_LC2_A17 & _LC4_A15
# _LC2_A17 & q6;
-- Node name is ':31' = 'q6'
-- Equation name is 'q6', location is LC7_A15, type is buried.
q6 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !_LC2_A17 & _LC6_A15
# _LC2_A17 & q7;
-- Node name is ':30' = 'q7'
-- Equation name is 'q7', location is LC2_A15, type is buried.
q7 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = _LC8_A15
# _LC1_A17 & q7
# _LC2_A17;
-- Node name is ':29' = 'q8'
-- Equation name is 'q8', location is LC8_C22, type is buried.
q8 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
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