📄 count60.rpt
字号:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 6/ 96( 6%) 0/ 48( 0%) 6/ 48( 12%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\11\k1\count60.rpt
count60
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CLK
Device-Specific Information: e:\11\k1\count60.rpt
count60
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 CLR
Device-Specific Information: e:\11\k1\count60.rpt
count60
** EQUATIONS **
CLK : INPUT;
CLR : INPUT;
EN : INPUT;
-- Node name is 'CO'
-- Equation name is 'CO', type is output
CO = _LC4_C23;
-- Node name is 'QH0'
-- Equation name is 'QH0', type is output
QH0 = _LC7_C23;
-- Node name is 'QH1'
-- Equation name is 'QH1', type is output
QH1 = _LC5_C23;
-- Node name is 'QH2'
-- Equation name is 'QH2', type is output
QH2 = _LC1_C23;
-- Node name is 'QH3'
-- Equation name is 'QH3', type is output
QH3 = _LC3_C23;
-- Node name is 'QL0'
-- Equation name is 'QL0', type is output
QL0 = _LC2_C14;
-- Node name is 'QL1'
-- Equation name is 'QL1', type is output
QL1 = _LC1_C14;
-- Node name is 'QL2'
-- Equation name is 'QL2', type is output
QL2 = _LC6_C14;
-- Node name is 'QL3'
-- Equation name is 'QL3', type is output
QL3 = _LC5_C14;
-- Node name is '|74160:1|:6' = '|74160:1|QA'
-- Equation name is '_LC2_C14', type is buried
_LC2_C14 = DFFE( _EQ001, GLOBAL( CLK), GLOBAL( CLR), VCC, VCC);
_EQ001 = EN & !_LC2_C14 & _LC4_C23
# !EN & _LC2_C14 & _LC4_C23;
-- Node name is '|74160:1|:7' = '|74160:1|QB'
-- Equation name is '_LC1_C14', type is buried
_LC1_C14 = DFFE( _EQ002, GLOBAL( CLK), GLOBAL( CLR), VCC, VCC);
_EQ002 = _LC1_C14 & _LC4_C23 & _LC5_C14
# _LC1_C14 & _LC4_C23 & _LC7_C14
# !_LC1_C14 & !_LC5_C14 & !_LC7_C14
# !_LC4_C23 & !_LC5_C14 & !_LC7_C14;
-- Node name is '|74160:1|:8' = '|74160:1|QC'
-- Equation name is '_LC6_C14', type is buried
_LC6_C14 = DFFE( _EQ003, GLOBAL( CLK), GLOBAL( CLR), VCC, VCC);
_EQ003 = _LC3_C14 & !_LC6_C14
# _LC3_C14 & !_LC4_C23
# !_LC3_C14 & _LC4_C23 & _LC6_C14;
-- Node name is '|74160:1|:9' = '|74160:1|QD'
-- Equation name is '_LC5_C14', type is buried
_LC5_C14 = DFFE( _EQ004, GLOBAL( CLK), GLOBAL( CLR), VCC, VCC);
_EQ004 = !_LC4_C14 & _LC4_C23 & _LC5_C14 & _LC7_C14
# _LC4_C14 & !_LC5_C14
# _LC4_C14 & !_LC7_C14
# _LC4_C14 & !_LC4_C23;
-- Node name is '|74160:1|:45' = '|74160:1|RCO'
-- Equation name is '_LC2_C23', type is buried
_LC2_C23 = LCELL( _EQ005);
_EQ005 = _LC5_C14 & !_LC7_C14;
-- Node name is '|74160:1|:25'
-- Equation name is '_LC3_C14', type is buried
_LC3_C14 = LCELL( _EQ006);
_EQ006 = EN & _LC1_C14 & _LC2_C14 & _LC4_C23;
-- Node name is '|74160:1|:46'
-- Equation name is '_LC4_C14', type is buried
_LC4_C14 = LCELL( _EQ007);
_EQ007 = _LC3_C14 & _LC6_C14;
-- Node name is '|74160:1|:65'
-- Equation name is '_LC7_C14', type is buried
!_LC7_C14 = _LC7_C14~NOT;
_LC7_C14~NOT = LCELL( _EQ008);
_EQ008 = EN & _LC2_C14;
-- Node name is '|74160:2|:6' = '|74160:2|QA'
-- Equation name is '_LC7_C23', type is buried
_LC7_C23 = DFFE( _EQ009, GLOBAL( CLK), GLOBAL( CLR), VCC, VCC);
_EQ009 = _LC2_C23 & _LC4_C23 & !_LC7_C23
# !_LC2_C23 & _LC4_C23 & _LC7_C23;
-- Node name is '|74160:2|:7' = '|74160:2|QB'
-- Equation name is '_LC5_C23', type is buried
_LC5_C23 = DFFE( _EQ010, GLOBAL( CLK), GLOBAL( CLR), VCC, VCC);
_EQ010 = !_LC3_C23 & !_LC5_C23 & _LC6_C23
# !_LC3_C23 & !_LC4_C23 & _LC6_C23
# _LC3_C23 & _LC4_C23 & _LC5_C23
# _LC4_C23 & _LC5_C23 & !_LC6_C23;
-- Node name is '|74160:2|:8' = '|74160:2|QC'
-- Equation name is '_LC1_C23', type is buried
_LC1_C23 = DFFE( _EQ011, GLOBAL( CLK), GLOBAL( CLR), VCC, VCC);
_EQ011 = !_LC1_C23 & _LC5_C23 & _LC6_C23
# !_LC4_C23 & _LC5_C23 & _LC6_C23
# _LC1_C23 & _LC4_C23 & !_LC5_C23
# _LC1_C23 & _LC4_C23 & !_LC6_C23;
-- Node name is '|74160:2|:9' = '|74160:2|QD'
-- Equation name is '_LC3_C23', type is buried
_LC3_C23 = DFFE( _EQ012, GLOBAL( CLK), GLOBAL( CLR), VCC, VCC);
_EQ012 = _LC3_C23 & _LC4_C23 & !_LC7_C23
# !_LC2_C23 & _LC3_C23 & _LC4_C23;
-- Node name is '|74160:2|~25~1'
-- Equation name is '_LC6_C23', type is buried
-- synthesized logic cell
_LC6_C23 = LCELL( _EQ013);
_EQ013 = _LC2_C23 & _LC4_C23 & _LC7_C23;
-- Node name is ':13'
-- Equation name is '_LC4_C23', type is buried
_LC4_C23 = LCELL( _EQ014);
_EQ014 = !_LC5_C14
# !_LC2_C14
# !_LC1_C23
# !_LC7_C23;
Project Information e:\11\k1\count60.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,619K
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