📄 count_top.rpt
字号:
# _LC1_D16 & _LC6_D18 & !_LC8_D18;
-- Node name is '|DISPLAY:18|:667'
-- Equation name is '_LC8_D23', type is buried
_LC8_D23 = LCELL( _EQ084);
_EQ084 = !_LC1_D13 & _LC6_D23
# !_LC1_D13 & _LC7_D23
# _LC1_D13 & _LC8_D24;
-- Node name is '|DISPLAY:18|~696~1'
-- Equation name is '_LC7_D13', type is buried
-- synthesized logic cell
_LC7_D13 = LCELL( _EQ085);
_EQ085 = !_LC1_D13 & !_LC2_D13;
-- Node name is '|DISPLAY:18|:712'
-- Equation name is '_LC3_D13', type is buried
_LC3_D13 = LCELL( _EQ086);
_EQ086 = _LC6_D18 & !_LC8_D18
# _LC6_D18 & !_LC6_D20
# !_LC5_D18 & !_LC6_D20
# !_LC6_D20 & !_LC8_D18;
-- Node name is '|DISPLAY:18|:869'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ087);
_EQ087 = !_LC2_D21 & !_LC3_D23 & !_LC8_D13 & !_LC8_D20;
-- Node name is '|DISPLAY:18|:874'
-- Equation name is '_LC3_B2', type is buried
!_LC3_B2 = _LC3_B2~NOT;
_LC3_B2~NOT = LCELL( _EQ088);
_EQ088 = _LC2_D21
# !_LC3_D23
# _LC8_D13
# _LC8_D20;
-- Node name is '|DISPLAY:18|:879'
-- Equation name is '_LC1_B12', type is buried
_LC1_B12 = LCELL( _EQ089);
_EQ089 = _LC2_D21 & !_LC3_D23 & !_LC8_D13 & !_LC8_D20;
-- Node name is '|DISPLAY:18|:889'
-- Equation name is '_LC4_B2', type is buried
!_LC4_B2 = _LC4_B2~NOT;
_LC4_B2~NOT = LCELL( _EQ090);
_EQ090 = _LC2_D21
# _LC3_D23
# _LC8_D13
# !_LC8_D20;
-- Node name is '|DISPLAY:18|:904'
-- Equation name is '_LC3_B12', type is buried
!_LC3_B12 = _LC3_B12~NOT;
_LC3_B12~NOT = LCELL( _EQ091);
_EQ091 = !_LC2_D21
# !_LC3_D23
# _LC8_D13
# !_LC8_D20;
-- Node name is '|DISPLAY:18|:919'
-- Equation name is '_LC8_B11', type is buried
!_LC8_B11 = _LC8_B11~NOT;
_LC8_B11~NOT = LCELL( _EQ092);
_EQ092 = !_LC2_D21
# _LC3_D23
# !_LC8_D13
# _LC8_D20;
-- Node name is '|DISPLAY:18|~1000~1'
-- Equation name is '_LC5_B11', type is buried
-- synthesized logic cell
_LC5_B11 = LCELL( _EQ093);
_EQ093 = !_LC2_D21 & _LC8_D13 & !_LC8_D20;
-- Node name is '|DISPLAY:18|:1050'
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = LCELL( _EQ094);
_EQ094 = _LC2_D21 & _LC8_D13
# _LC2_D21 & !_LC8_D20
# _LC2_D21 & !_LC3_D23
# _LC8_D13 & !_LC8_D20
# _LC3_D23 & _LC8_D13
# !_LC3_D23 & !_LC8_D13 & _LC8_D20
# !_LC2_D21 & _LC3_D23 & _LC8_D20;
-- Node name is '|DISPLAY:18|:1099'
-- Equation name is '_LC4_B12', type is buried
_LC4_B12 = LCELL( _EQ095);
_EQ095 = _LC8_D13 & !_LC8_D20
# !_LC3_D23 & _LC8_D13
# !_LC2_D21 & !_LC3_D23
# !_LC2_D21 & !_LC8_D13 & _LC8_D20
# !_LC3_D23 & _LC8_D20;
-- Node name is '|DISPLAY:18|:1144'
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = LCELL( _EQ096);
_EQ096 = _LC1_B12
# !_LC4_B2 & _LC8_B12;
-- Node name is '|DISPLAY:18|~1146~1'
-- Equation name is '_LC8_B12', type is buried
-- synthesized logic cell
_LC8_B12 = LCELL( _EQ097);
_EQ097 = !_LC3_D23 & _LC8_D13 & !_LC8_D20
# !_LC2_D21 & _LC8_D13 & _LC8_D20
# _LC2_D21 & _LC8_D13 & !_LC8_D20
# _LC2_D21 & !_LC3_D23 & _LC8_D20
# !_LC2_D21 & !_LC3_D23 & _LC8_D13;
-- Node name is '|DISPLAY:18|:1150'
-- Equation name is '_LC5_B2', type is buried
_LC5_B2 = LCELL( _EQ098);
_EQ098 = !_LC3_B2 & _LC8_B2
# _LC1_B2;
-- Node name is '|DISPLAY:18|:1168'
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = LCELL( _EQ099);
_EQ099 = _LC2_D21 & _LC3_D23 & _LC8_D13 & !_LC8_D20
# !_LC3_D23 & _LC8_D13 & _LC8_D20
# !_LC2_D21 & _LC8_D13 & _LC8_D20;
-- Node name is '|DISPLAY:18|:1177'
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ100);
_EQ100 = _LC5_B11
# _LC6_B11 & !_LC8_B11;
-- Node name is '|DISPLAY:18|:1194'
-- Equation name is '_LC7_B2', type is buried
_LC7_B2 = LCELL( _EQ101);
_EQ101 = _LC3_B11 & !_LC4_B2
# _LC1_B11 & !_LC3_B12 & !_LC4_B2;
-- Node name is '|DISPLAY:18|:1201'
-- Equation name is '_LC6_B2', type is buried
_LC6_B2 = LCELL( _EQ102);
_EQ102 = _LC1_B2
# _LC2_B2 & !_LC3_B2
# !_LC3_B2 & _LC7_B2;
-- Node name is '|DISPLAY:18|:1252'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ103);
_EQ103 = !_LC2_D21 & !_LC8_D13
# !_LC8_D13 & _LC8_D20
# !_LC2_D21 & _LC3_D23
# _LC8_D13 & !_LC8_D20
# !_LC2_D21 & !_LC8_D20
# _LC3_D23 & !_LC8_D20
# _LC3_D23 & !_LC8_D13;
-- Node name is '|DISPLAY:18|:1303'
-- Equation name is '_LC5_B12', type is buried
_LC5_B12 = LCELL( _EQ104);
_EQ104 = !_LC2_D21 & !_LC3_D23 & !_LC8_D13
# !_LC8_D13 & !_LC8_D20
# !_LC2_D21 & _LC3_D23 & _LC8_D13
# !_LC3_D23 & !_LC8_D20
# !_LC2_D21 & !_LC8_D20
# _LC2_D21 & _LC3_D23 & !_LC8_D13;
-- Node name is '|DISPLAY:18|~1339~1'
-- Equation name is '_LC3_B11', type is buried
-- synthesized logic cell
_LC3_B11 = LCELL( _EQ105);
_EQ105 = !_LC2_D21 & _LC3_D23 & !_LC8_D13 & _LC8_D20
# _LC2_D21 & !_LC3_D23 & !_LC8_D13 & _LC8_D20;
-- Node name is '|DISPLAY:18|~1348~1'
-- Equation name is '_LC2_B2', type is buried
-- synthesized logic cell
_LC2_B2 = LCELL( _EQ106);
_EQ106 = _LC2_D21 & !_LC8_D13 & !_LC8_D20;
-- Node name is '|DISPLAY:18|:1354'
-- Equation name is '_LC7_B11', type is buried
_LC7_B11 = LCELL( _EQ107);
_EQ107 = _LC3_D23 & !_LC8_D13 & _LC8_D20
# !_LC3_D23 & !_LC8_D20
# !_LC2_D21 & _LC8_D13 & !_LC8_D20
# _LC2_D21 & !_LC8_D13
# _LC2_D21 & !_LC3_D23
# !_LC3_D23 & _LC8_D13;
-- Node name is '|js:4|:2' = '|js:4|OUT'
-- Equation name is '_LC2_D22', type is buried
_LC2_D22 = LCELL( _EQ108);
_EQ108 = HOUR_K & _LC2_D17
# CLK & !HOUR_K;
-- Node name is '|js:6|:2' = '|js:6|OUT'
-- Equation name is '_LC4_D16', type is buried
_LC4_D16 = LCELL( _EQ109);
_EQ109 = _LC6_D24 & MIN_K
# CLK & !MIN_K;
Project Information h:\11\k1\count_top.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:04
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,231K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -