📄 count_top.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: h:\11\k1\count_top.rpt
count_top
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
90 - - C -- OUTPUT 0 1 0 0 L0
91 - - C -- OUTPUT 0 1 0 0 L1
92 - - C -- OUTPUT 0 1 0 0 L2
95 - - B -- OUTPUT 0 1 0 0 L3
96 - - B -- OUTPUT 0 1 0 0 L4
97 - - B -- OUTPUT 0 1 0 0 L5
98 - - B -- OUTPUT 0 1 0 0 L6
20 - - D -- OUTPUT 0 1 0 0 SEL0
21 - - D -- OUTPUT 0 1 0 0 SEL1
22 - - D -- OUTPUT 0 1 0 0 SEL2
99 - - B -- OUTPUT 0 1 0 0 spk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: h:\11\k1\count_top.rpt
count_top
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - D 02 DFFE 0 2 0 1 |bs:1|:1
- 1 - D 02 AND2 1 1 1 0 |bs:1|SPK (|bs:1|:4)
- 4 - D 19 OR2 0 3 0 11 |count24:2|CO (|count24:2|:3)
- 6 - D 22 DFFE 2 2 0 6 |count24:2|74160:1|QA (|count24:2|74160:1|:6)
- 4 - D 22 DFFE 1 4 0 3 |count24:2|74160:1|QB (|count24:2|74160:1|:7)
- 3 - D 22 DFFE 1 3 0 2 |count24:2|74160:1|QC (|count24:2|74160:1|:8)
- 1 - D 22 DFFE 1 4 0 3 |count24:2|74160:1|QD (|count24:2|74160:1|:9)
- 7 - D 22 AND2 1 3 0 2 |count24:2|74160:1|:25
- 1 - D 19 AND2 1 2 0 3 |count24:2|74160:1|RCO (|count24:2|74160:1|:45)
- 8 - D 22 OR2 s 1 2 0 1 |count24:2|74160:1|~49~1
- 5 - D 22 AND2 s 1 2 0 1 |count24:2|74160:1|~50~1
- 5 - D 19 DFFE 1 3 0 3 |count24:2|74160:2|QA (|count24:2|74160:2|:6)
- 2 - D 19 DFFE 1 4 0 4 |count24:2|74160:2|QB (|count24:2|74160:2|:7)
- 3 - D 19 DFFE 1 4 0 2 |count24:2|74160:2|QC (|count24:2|74160:2|:8)
- 8 - D 19 DFFE 1 5 0 3 |count24:2|74160:2|QD (|count24:2|74160:2|:9)
- 6 - D 19 OR2 0 4 0 1 |count24:2|74160:2|:49
- 7 - D 19 AND2 s 0 3 0 3 |count24:2|74160:2|~50~1
- 6 - D 24 OR2 0 4 0 12 |count60:3|CO (|count60:3|:13)
- 2 - D 16 DFFE 3 1 0 4 |count60:3|74160:1|QA (|count60:3|74160:1|:6)
- 3 - D 24 DFFE 2 3 0 2 |count60:3|74160:1|QB (|count60:3|74160:1|:7)
- 1 - D 15 DFFE 2 2 0 2 |count60:3|74160:1|QC (|count60:3|74160:1|:8)
- 2 - D 24 DFFE 2 3 0 6 |count60:3|74160:1|QD (|count60:3|74160:1|:9)
- 1 - D 24 AND2 1 3 0 2 |count60:3|74160:1|:25
- 1 - D 14 OR2 ! 0 2 0 1 |count60:3|74160:1|RCO (|count60:3|74160:1|:45)
- 4 - D 15 AND2 0 2 0 1 |count60:3|74160:1|:46
- 4 - D 23 OR2 1 1 0 5 |count60:3|74160:1|:65
- 8 - D 24 DFFE 2 3 0 4 |count60:3|74160:2|QA (|count60:3|74160:2|:6)
- 4 - D 24 DFFE 2 3 0 2 |count60:3|74160:2|QB (|count60:3|74160:2|:7)
- 5 - D 24 DFFE 2 3 0 2 |count60:3|74160:2|QC (|count60:3|74160:2|:8)
- 5 - D 14 DFFE 2 3 0 2 |count60:3|74160:2|QD (|count60:3|74160:2|:9)
- 7 - D 24 AND2 s 0 4 0 2 |count60:3|74160:2|~50~1
- 2 - D 17 OR2 0 4 0 12 |count60:5|CO (|count60:5|:13)
- 1 - D 16 DFFE 2 2 0 4 |count60:5|74160:1|QA (|count60:5|74160:1|:6)
- 5 - D 16 DFFE 1 4 0 2 |count60:5|74160:1|QB (|count60:5|74160:1|:7)
- 6 - D 16 DFFE 1 3 0 2 |count60:5|74160:1|QC (|count60:5|74160:1|:8)
- 4 - D 17 DFFE 1 4 0 6 |count60:5|74160:1|QD (|count60:5|74160:1|:9)
- 7 - D 16 AND2 1 3 0 2 |count60:5|74160:1|:25
- 6 - D 17 OR2 ! 0 2 0 1 |count60:5|74160:1|RCO (|count60:5|74160:1|:45)
- 8 - D 16 AND2 0 2 0 1 |count60:5|74160:1|:46
- 3 - D 16 OR2 1 1 0 5 |count60:5|74160:1|:65
- 1 - D 17 DFFE 1 4 0 4 |count60:5|74160:2|QA (|count60:5|74160:2|:6)
- 5 - D 17 DFFE 1 4 0 2 |count60:5|74160:2|QB (|count60:5|74160:2|:7)
- 3 - D 17 DFFE 1 4 0 2 |count60:5|74160:2|QC (|count60:5|74160:2|:8)
- 8 - D 17 DFFE 1 4 0 2 |count60:5|74160:2|QD (|count60:5|74160:2|:9)
- 7 - D 17 AND2 s 0 4 0 2 |count60:5|74160:2|~50~1
- 1 - D 18 OR2 ! 0 3 0 4 |DISPLAY:18|LPM_ADD_SUB:129|addcore:adder|:67
- 8 - D 18 DFFE 1 3 0 22 |DISPLAY:18|q5 (|DISPLAY:18|:44)
- 6 - D 18 DFFE 1 2 0 23 |DISPLAY:18|q4 (|DISPLAY:18|:45)
- 5 - D 18 DFFE 1 2 0 24 |DISPLAY:18|q3 (|DISPLAY:18|:46)
- 3 - D 18 DFFE 1 3 0 1 |DISPLAY:18|q2 (|DISPLAY:18|:47)
- 7 - D 18 DFFE 1 2 0 2 |DISPLAY:18|q1 (|DISPLAY:18|:48)
- 4 - D 18 DFFE 1 0 0 3 |DISPLAY:18|q0 (|DISPLAY:18|:49)
- 8 - D 13 DFFE 1 3 0 16 |DISPLAY:18|num3~115 (|DISPLAY:18|:53)
- 8 - D 20 DFFE 1 3 0 16 |DISPLAY:18|num2~115 (|DISPLAY:18|:54)
- 2 - D 21 DFFE 1 3 0 16 |DISPLAY:18|num1~115 (|DISPLAY:18|:55)
- 3 - D 23 DFFE 1 3 0 14 |DISPLAY:18|num0 (|DISPLAY:18|:56)
- 6 - D 13 DFFE 1 3 1 0 |DISPLAY:18|sel2 (|DISPLAY:18|:57)
- 5 - D 13 DFFE 1 3 1 0 |DISPLAY:18|sel1 (|DISPLAY:18|:58)
- 4 - D 13 DFFE 1 1 1 0 |DISPLAY:18|sel0 (|DISPLAY:18|:59)
- 2 - D 18 OR2 ! 0 4 0 3 |DISPLAY:18|:92
- 2 - D 13 OR2 ! 0 3 0 6 |DISPLAY:18|:331
- 1 - D 13 OR2 ! 0 3 0 6 |DISPLAY:18|:338
- 6 - D 20 OR2 ! 0 3 0 5 |DISPLAY:18|:359
- 3 - D 14 AND2 0 4 0 1 |DISPLAY:18|:563
- 4 - D 14 OR2 s 0 4 0 1 |DISPLAY:18|~568~1
- 6 - D 14 OR2 0 4 0 1 |DISPLAY:18|:574
- 7 - D 14 OR2 0 4 0 1 |DISPLAY:18|:582
- 8 - D 14 OR2 s 0 4 0 1 |DISPLAY:18|~586~1
- 2 - D 14 OR2 0 4 0 1 |DISPLAY:18|:592
- 2 - D 20 AND2 0 4 0 1 |DISPLAY:18|:605
- 1 - D 20 OR2 s 0 4 0 1 |DISPLAY:18|~607~1
- 3 - D 20 OR2 0 4 0 1 |DISPLAY:18|:610
- 4 - D 20 OR2 0 4 0 1 |DISPLAY:18|:615
- 5 - D 20 OR2 s 0 4 0 1 |DISPLAY:18|~616~1
- 7 - D 20 OR2 0 4 0 1 |DISPLAY:18|:619
- 1 - D 21 OR2 0 4 0 1 |DISPLAY:18|:630
- 3 - D 21 OR2 s 0 4 0 1 |DISPLAY:18|~631~1
- 4 - D 21 OR2 0 4 0 1 |DISPLAY:18|:634
- 5 - D 21 OR2 0 4 0 1 |DISPLAY:18|:639
- 6 - D 21 OR2 s 0 4 0 1 |DISPLAY:18|~640~1
- 7 - D 21 OR2 0 4 0 1 |DISPLAY:18|:643
- 1 - D 23 AND2 0 4 0 1 |DISPLAY:18|:653
- 2 - D 23 OR2 s 0 4 0 1 |DISPLAY:18|~655~1
- 5 - D 23 OR2 0 4 0 1 |DISPLAY:18|:658
- 6 - D 23 OR2 0 4 0 1 |DISPLAY:18|:663
- 7 - D 23 OR2 s 0 4 0 1 |DISPLAY:18|~664~1
- 8 - D 23 OR2 0 4 0 1 |DISPLAY:18|:667
- 7 - D 13 AND2 s 0 2 0 1 |DISPLAY:18|~696~1
- 3 - D 13 OR2 0 4 0 1 |DISPLAY:18|:712
- 1 - B 02 AND2 0 4 0 2 |DISPLAY:18|:869
- 3 - B 02 OR2 ! 0 4 0 2 |DISPLAY:18|:874
- 1 - B 12 AND2 0 4 0 1 |DISPLAY:18|:879
- 4 - B 02 OR2 ! 0 4 0 2 |DISPLAY:18|:889
- 3 - B 12 OR2 ! 0 4 0 1 |DISPLAY:18|:904
- 8 - B 11 OR2 ! 0 4 0 1 |DISPLAY:18|:919
- 5 - B 11 AND2 s 0 3 0 1 |DISPLAY:18|~1000~1
- 2 - B 11 OR2 0 4 1 0 |DISPLAY:18|:1050
- 4 - B 12 OR2 0 4 1 0 |DISPLAY:18|:1099
- 8 - B 02 OR2 0 3 0 1 |DISPLAY:18|:1144
- 8 - B 12 OR2 s 0 4 0 1 |DISPLAY:18|~1146~1
- 5 - B 02 OR2 0 3 1 0 |DISPLAY:18|:1150
- 6 - B 11 OR2 0 4 0 1 |DISPLAY:18|:1168
- 1 - B 11 OR2 0 3 0 1 |DISPLAY:18|:1177
- 7 - B 02 OR2 0 4 0 1 |DISPLAY:18|:1194
- 6 - B 02 OR2 0 4 1 0 |DISPLAY:18|:1201
- 4 - B 11 OR2 0 4 1 0 |DISPLAY:18|:1252
- 5 - B 12 OR2 0 4 1 0 |DISPLAY:18|:1303
- 3 - B 11 OR2 s 0 4 0 1 |DISPLAY:18|~1339~1
- 2 - B 02 AND2 s 0 3 0 1 |DISPLAY:18|~1348~1
- 7 - B 11 OR2 0 4 1 0 |DISPLAY:18|:1354
- 2 - D 22 OR2 2 1 0 8 |js:4|OUT (|js:4|:2)
- 4 - D 16 OR2 2 1 0 8 |js:6|OUT (|js:6|:2)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: h:\11\k1\count_top.rpt
count_top
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
B: 6/ 96( 6%) 10/ 48( 20%) 0/ 48( 0%) 2/16( 12%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
D: 23/ 96( 23%) 0/ 48( 0%) 34/ 48( 70%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
E: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: h:\11\k1\count_top.rpt
count_top
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 13 disclk
LCELL 12 |count60:5|CO
INPUT 10 CLK
LCELL 8 |js:4|OUT
LCELL 8 |js:6|OUT
Device-Specific Information: h:\11\k1\count_top.rpt
count_top
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 24 CLR
LCELL 12 |count60:3|CO
Device-Specific Information: h:\11\k1\count_top.rpt
count_top
** EQUATIONS **
CLK : INPUT;
CLR : INPUT;
disclk : INPUT;
EN : INPUT;
HOUR_K : INPUT;
MIN_K : INPUT;
SPECLK : INPUT;
-- Node name is 'L0'
-- Equation name is 'L0', type is output
L0 = _LC7_B11;
-- Node name is 'L1'
-- Equation name is 'L1', type is output
L1 = _LC5_B12;
-- Node name is 'L2'
-- Equation name is 'L2', type is output
L2 = _LC4_B11;
-- Node name is 'L3'
-- Equation name is 'L3', type is output
L3 = _LC6_B2;
-- Node name is 'L4'
-- Equation name is 'L4', type is output
L4 = _LC5_B2;
-- Node name is 'L5'
-- Equation name is 'L5', type is output
L5 = _LC4_B12;
-- Node name is 'L6'
-- Equation name is 'L6', type is output
L6 = _LC2_B11;
-- Node name is 'SEL0'
-- Equation name is 'SEL0', type is output
SEL0 = _LC4_D13;
-- Node name is 'SEL1'
-- Equation name is 'SEL1', type is output
SEL1 = _LC5_D13;
-- Node name is 'SEL2'
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