hzxs.rpt

以FPGA芯片为核心

!_LC4_A12 = _LC4_A12~NOT;
_LC4_A12~NOT = LCELL( _EQ022);
  _EQ022 = !NEXT10
         #  NEXT11;

-- Node name is '~5643~1' 
-- Equation name is '~5643~1', location is LC5_D9, type is buried.
-- synthesized logic cell 
_LC5_D9  = LCELL( _EQ023);
  _EQ023 =  LIE0 & !LIE2 &  LIE3
         #  LIE1 & !LIE2 &  LIE3;

-- Node name is '~5643~2' 
-- Equation name is '~5643~2', location is LC7_A6, type is buried.
-- synthesized logic cell 
_LC7_A6  = LCELL( _EQ024);
  _EQ024 = !_LC2_A6 &  _LC3_A1 &  _LC4_A12 &  _LC6_A6;

-- Node name is ':5643' 
-- Equation name is '_LC8_A12', type is buried 
_LC8_A12 = LCELL( _EQ025);
  _EQ025 = !NEXT10 & !NEXT11;

-- Node name is ':5668' 
-- Equation name is '_LC7_A9', type is buried 
_LC7_A9  = LCELL( _EQ026);
  _EQ026 = !_LC4_A1 &  _LC4_A12 &  _LC8_A1
         #  _LC3_A9 & !_LC4_A1 &  _LC4_A12;

-- Node name is ':5669' 
-- Equation name is '_LC3_A12', type is buried 
_LC3_A12 = LCELL( _EQ027);
  _EQ027 =  _LC2_A1 & !_LC4_A12 &  NEXT10
         #  _LC2_A1 & !_LC4_A12 & !NEXT11;

-- Node name is ':5670' 
-- Equation name is '_LC2_A9', type is buried 
_LC2_A9  = LCELL( _EQ028);
  _EQ028 =  _LC5_A9
         #  _LC7_A9 & !_LC8_A12
         #  _LC3_A12 & !_LC8_A12;

-- Node name is '~5671~1' 
-- Equation name is '~5671~1', location is LC3_A6, type is buried.
-- synthesized logic cell 
_LC3_A6  = LCELL( _EQ029);
  _EQ029 = !_LC2_A6 &  _LC5_A6;

-- Node name is '~5671~2' 
-- Equation name is '~5671~2', location is LC5_A3, type is buried.
-- synthesized logic cell 
_LC5_A3  = LCELL( _EQ030);
  _EQ030 =  _LC3_A1 &  _LC8_A12;

-- Node name is ':5671' 
-- Equation name is '_LC5_A9', type is buried 
_LC5_A9  = LCELL( _EQ031);
  _EQ031 =  _LC3_A6 &  _LC3_D9
         #  _LC3_A6 &  _LC6_A9
         #  _LC3_A6 &  _LC6_A10;

-- Node name is ':5682' 
-- Equation name is '_LC4_A3', type is buried 
_LC4_A3  = LCELL( _EQ032);
  _EQ032 =  _LC3_A3 &  _LC3_D9 &  _LC6_A3
         #  _LC8_A9;

-- Node name is '~5683~1' 
-- Equation name is '~5683~1', location is LC7_A1, type is buried.
-- synthesized logic cell 
_LC7_A1  = LCELL( _EQ033);
  _EQ033 = !_LC4_A1 & !_LC8_A1;

-- Node name is '~5683~2' 
-- Equation name is '~5683~2', location is LC3_A3, type is buried.
-- synthesized logic cell 
_LC3_A3  = LCELL( _EQ034);
  _EQ034 = !_LC4_A1 & !_LC8_A1 &  _LC8_A12;

-- Node name is ':5684' 
-- Equation name is '_LC8_A9', type is buried 
_LC8_A9  = LCELL( _EQ035);
  _EQ035 =  _LC3_A12 & !_LC8_A12
         #  _LC2_A1 &  _LC4_A12 & !_LC8_A12;

-- Node name is ':5694' 
-- Equation name is '_LC7_A3', type is buried 
_LC7_A3  = LCELL( _EQ036);
  _EQ036 = !_LC4_A1 &  _LC8_A3 &  _LC8_A12
         #  _LC8_A9;

-- Node name is ':5706' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = LCELL( _EQ037);
  _EQ037 =  _LC3_A3 &  _LC6_A1
         #  _LC1_A10 &  _LC3_A3
         #  _LC8_A9;

-- Node name is ':5718' 
-- Equation name is '_LC2_A3', type is buried 
_LC2_A3  = LCELL( _EQ038);
  _EQ038 =  _LC8_A9
         #  _LC1_D9 &  _LC5_A3
         #  _LC1_A10 &  _LC5_A3;

-- Node name is '~5726~1' 
-- Equation name is '~5726~1', location is LC6_A6, type is buried.
-- synthesized logic cell 
_LC6_A6  = LCELL( _EQ039);
  _EQ039 = !_LC1_A10 & !_LC1_D9 &  _LC6_A9;

-- Node name is '~5728~1' 
-- Equation name is '~5728~1', location is LC3_A1, type is buried.
-- synthesized logic cell 
_LC3_A1  = LCELL( _EQ040);
  _EQ040 = !_LC6_A1 &  _LC7_A1;

-- Node name is '~5730~1' 
-- Equation name is '~5730~1', location is LC6_D9, type is buried.
-- synthesized logic cell 
_LC6_D9  = LCELL( _EQ041);
  _EQ041 = !LIE0 & !LIE1 &  LIE2 & !LIE3
         # !LIE0 &  LIE1 &  LIE2 &  LIE3;

-- Node name is '~5730~2' 
-- Equation name is '~5730~2', location is LC2_D9, type is buried.
-- synthesized logic cell 
_LC2_D9  = LCELL( _EQ042);
  _EQ042 = !_LC4_A12 &  _LC5_D9 & !_LC6_A12
         # !_LC4_A12 &  _LC6_A12 &  _LC6_D9;

-- Node name is '~5730~3' 
-- Equation name is '~5730~3', location is LC8_A6, type is buried.
-- synthesized logic cell 
_LC8_A6  = LCELL( _EQ043);
  _EQ043 =  _LC2_D9 & !_LC4_A1 & !_LC8_A12
         #  _LC7_A6 & !_LC8_A12;

-- Node name is ':5730' 
-- Equation name is '_LC4_A6', type is buried 
_LC4_A6  = LCELL( _EQ044);
  _EQ044 =  _LC8_A6
         #  _LC2_A6 &  _LC5_A6
         #  _LC1_A10 &  _LC5_A6;

-- Node name is ':5737' 
-- Equation name is '_LC8_A7', type is buried 
_LC8_A7  = LCELL( _EQ045);
  _EQ045 =  _LC6_A12 &  _LC7_A1 &  _LC7_A7
         #  _LC6_A1 &  _LC6_A12 &  _LC7_A1;

-- Node name is ':5739' 
-- Equation name is '_LC6_A7', type is buried 
_LC6_A7  = LCELL( _EQ046);
  _EQ046 =  _LC2_A1 &  _LC4_A12
         #  _LC2_A1 & !_LC6_A12
         # !_LC4_A12 &  _LC8_A7;

-- Node name is ':5742' 
-- Equation name is '_LC1_A6', type is buried 
_LC1_A6  = LCELL( _EQ047);
  _EQ047 =  _LC6_A7 & !_LC8_A12
         #  _LC1_A10 &  _LC8_A12;

-- Node name is ':5743' 
-- Equation name is '_LC2_D12', type is buried 
_LC2_D12 = LCELL( _EQ048);
  _EQ048 =  _LC1_A10 &  _LC8_A12;

-- Node name is ':5749' 
-- Equation name is '_LC1_A3', type is buried 
_LC1_A3  = LCELL( _EQ049);
  _EQ049 =  _LC1_D9 &  _LC3_A1 &  _LC6_A12
         #  _LC3_A1 &  _LC6_A10 &  _LC6_A12;

-- Node name is ':5754' 
-- Equation name is '_LC2_A7', type is buried 
_LC2_A7  = LCELL( _EQ050);
  _EQ050 =  _LC1_A12
         #  _LC2_A1 &  _LC3_A6
         #  _LC1_A10 &  _LC3_A6;

-- Node name is '~5755~1' 
-- Equation name is '~5755~1', location is LC5_A6, type is buried.
-- synthesized logic cell 
_LC5_A6  = LCELL( _EQ051);
  _EQ051 = !_LC1_D9 &  _LC3_A1 &  _LC8_A12;

-- Node name is ':5756' 
-- Equation name is '_LC1_A12', type is buried 
_LC1_A12 = LCELL( _EQ052);
  _EQ052 =  _LC2_A1 &  NEXT10
         #  _LC1_A3 &  NEXT11;

-- Node name is ':5760' 
-- Equation name is '_LC3_A7', type is buried 
_LC3_A7  = LCELL( _EQ053);
  _EQ053 =  _LC2_A1 & !_LC6_A12
         #  _LC3_A1 &  _LC4_D9 &  _LC6_A12;

-- Node name is '~5761~1' 
-- Equation name is '~5761~1', location is LC4_D9, type is buried.
-- synthesized logic cell 
_LC4_D9  = LCELL( _EQ054);
  _EQ054 =  LIE0 &  LIE1 & !LIE2 &  LIE3
         #  LIE0 &  LIE1 &  LIE2 & !LIE3;

-- Node name is ':5766' 
-- Equation name is '_LC4_A7', type is buried 
_LC4_A7  = LCELL( _EQ055);
  _EQ055 =  _LC5_A7
         #  _LC1_A7 &  _LC3_A6
         #  _LC1_A10 &  _LC3_A6;

-- Node name is ':5768' 
-- Equation name is '_LC5_A7', type is buried 
_LC5_A7  = LCELL( _EQ056);
  _EQ056 =  _LC2_A1 &  _LC4_A12 & !_LC8_A12
         #  _LC3_A7 & !_LC4_A12 & !_LC8_A12;

-- Node name is ':5778' 
-- Equation name is '_LC1_A9', type is buried 
_LC1_A9  = LCELL( _EQ057);
  _EQ057 =  _LC3_A6 &  _LC4_A9
         #  _LC1_A10 &  _LC3_A6
         #  _LC2_A12;

-- Node name is ':5780' 
-- Equation name is '_LC2_A12', type is buried 
_LC2_A12 = LCELL( _EQ058);
  _EQ058 =  _LC1_A7 & !NEXT10 &  NEXT11
         #  _LC2_A1 &  NEXT10;

-- Node name is ':5784' 
-- Equation name is '_LC2_A10', type is buried 
_LC2_A10 = LCELL( _EQ059);
  _EQ059 =  _LC2_A1 &  _LC6_A12
         #  _LC3_A9 & !_LC6_A12 &  _LC7_A1;

-- Node name is ':5790' 
-- Equation name is '_LC3_A10', type is buried 
_LC3_A10 = LCELL( _EQ060);
  _EQ060 =  _LC3_A6 &  _LC6_A10
         #  _LC1_A10 &  _LC3_A6
         #  _LC7_A10;

-- Node name is ':5792' 
-- Equation name is '_LC7_A10', type is buried 
_LC7_A10 = LCELL( _EQ061);
  _EQ061 =  _LC2_A1 &  _LC4_A12 & !_LC8_A12
         #  _LC2_A10 & !_LC4_A12 & !_LC8_A12;

-- Node name is ':5802' 
-- Equation name is '_LC8_D9', type is buried 
_LC8_D9  = LCELL( _EQ062);
  _EQ062 =  _LC1_A10 &  _LC8_A12
         #  _LC1_A10 &  _LC6_A12;



Project Information                                 f:\eda\45\k6\hzxs\hzxs.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,899K