📄 hzxs.rpt
字号:
- 3 - A 09 OR2 0 4 0 2 :5480
- 6 - A 12 AND2 0 2 0 7 :5627
- 4 - A 12 OR2 ! 0 2 0 8 :5635
- 5 - D 09 OR2 s 0 4 0 1 ~5643~1
- 7 - A 06 AND2 s 0 4 0 1 ~5643~2
- 8 - A 12 AND2 0 2 0 12 :5643
- 7 - A 09 OR2 0 4 0 1 :5668
- 3 - A 12 OR2 0 4 0 2 :5669
- 2 - A 09 OR2 0 4 1 0 :5670
- 3 - A 06 AND2 s 0 2 0 5 ~5671~1
- 5 - A 03 AND2 s 0 2 0 1 ~5671~2
- 5 - A 09 OR2 0 4 0 1 :5671
- 4 - A 03 OR2 0 4 1 0 :5682
- 7 - A 01 AND2 s 0 2 0 3 ~5683~1
- 3 - A 03 AND2 s 0 3 0 2 ~5683~2
- 8 - A 09 OR2 0 4 0 4 :5684
- 7 - A 03 OR2 0 4 1 0 :5694
- 1 - A 01 OR2 0 4 1 0 :5706
- 2 - A 03 OR2 0 4 1 0 :5718
- 6 - A 06 AND2 s 0 3 0 1 ~5726~1
- 3 - A 01 AND2 s 0 2 0 5 ~5728~1
- 6 - D 09 OR2 s 0 4 0 1 ~5730~1
- 2 - D 09 OR2 s 0 4 0 1 ~5730~2
- 8 - A 06 OR2 s 0 4 0 1 ~5730~3
- 4 - A 06 OR2 0 4 1 0 :5730
- 8 - A 07 OR2 0 4 0 1 :5737
- 6 - A 07 OR2 0 4 0 1 :5739
- 1 - A 06 OR2 0 3 1 0 :5742
- 2 - D 12 AND2 0 2 1 0 :5743
- 1 - A 03 OR2 0 4 0 1 :5749
- 2 - A 07 OR2 0 4 1 0 :5754
- 5 - A 06 AND2 s 0 3 0 2 ~5755~1
- 1 - A 12 OR2 0 4 0 1 :5756
- 3 - A 07 OR2 0 4 0 1 :5760
- 4 - D 09 OR2 s 0 4 0 1 ~5761~1
- 4 - A 07 OR2 0 4 1 0 :5766
- 5 - A 07 OR2 0 4 0 1 :5768
- 1 - A 09 OR2 0 4 1 0 :5778
- 2 - A 12 OR2 0 4 0 1 :5780
- 2 - A 10 OR2 0 4 0 1 :5784
- 3 - A 10 OR2 0 4 1 0 :5790
- 7 - A 10 OR2 0 4 0 1 :5792
- 8 - D 09 OR2 0 3 1 0 :5802
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\eda\45\k6\hzxs\hzxs.rpt
hzxs
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 25/ 48( 52%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 4/ 96( 4%) 5/ 48( 10%) 0/ 48( 0%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
E: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
F: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 9/24( 37%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
10: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\eda\45\k6\hzxs\hzxs.rpt
hzxs
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 CLK1
INPUT 2 CLK
Device-Specific Information: f:\eda\45\k6\hzxs\hzxs.rpt
hzxs
** EQUATIONS **
CLK : INPUT;
CLK1 : INPUT;
-- Node name is ':28' = 'LIE0'
-- Equation name is 'LIE0', location is LC4_A10, type is buried.
LIE0 = DFFE(!LIE0, CLK1, VCC, VCC, VCC);
-- Node name is ':27' = 'LIE1'
-- Equation name is 'LIE1', location is LC5_A1, type is buried.
LIE1 = DFFE( _EQ001, CLK1, VCC, VCC, VCC);
_EQ001 = !LIE0 & LIE1
# LIE0 & !LIE1;
-- Node name is ':26' = 'LIE2'
-- Equation name is 'LIE2', location is LC5_A10, type is buried.
LIE2 = DFFE( _EQ002, CLK1, VCC, VCC, VCC);
_EQ002 = !LIE1 & LIE2
# !LIE0 & LIE2
# LIE0 & LIE1 & !LIE2;
-- Node name is ':25' = 'LIE3'
-- Equation name is 'LIE3', location is LC8_A10, type is buried.
LIE3 = DFFE( _EQ003, CLK1, VCC, VCC, VCC);
_EQ003 = LIE0 & LIE1 & LIE2 & !LIE3
# !LIE1 & LIE3
# !LIE0 & LIE3
# !LIE2 & LIE3;
-- Node name is 'L0'
-- Equation name is 'L0', type is output
L0 = GND;
-- Node name is 'L1'
-- Equation name is 'L1', type is output
L1 = _LC2_D12;
-- Node name is 'L2'
-- Equation name is 'L2', type is output
L2 = _LC8_D9;
-- Node name is 'L3'
-- Equation name is 'L3', type is output
L3 = _LC3_A10;
-- Node name is 'L4'
-- Equation name is 'L4', type is output
L4 = _LC1_A9;
-- Node name is 'L5'
-- Equation name is 'L5', type is output
L5 = _LC4_A7;
-- Node name is 'L6'
-- Equation name is 'L6', type is output
L6 = _LC2_A7;
-- Node name is 'L7'
-- Equation name is 'L7', type is output
L7 = _LC1_A6;
-- Node name is 'L8'
-- Equation name is 'L8', type is output
L8 = _LC4_A6;
-- Node name is 'L9'
-- Equation name is 'L9', type is output
L9 = _LC2_A3;
-- Node name is 'L10'
-- Equation name is 'L10', type is output
L10 = _LC1_A1;
-- Node name is 'L11'
-- Equation name is 'L11', type is output
L11 = _LC7_A3;
-- Node name is 'L12'
-- Equation name is 'L12', type is output
L12 = _LC4_A3;
-- Node name is 'L13'
-- Equation name is 'L13', type is output
L13 = _LC2_A9;
-- Node name is 'L14'
-- Equation name is 'L14', type is output
L14 = GND;
-- Node name is 'L15'
-- Equation name is 'L15', type is output
L15 = GND;
-- Node name is ':24' = 'NEXT10'
-- Equation name is 'NEXT10', location is LC7_A12, type is buried.
NEXT10 = DFFE(!NEXT10, CLK, VCC, VCC, VCC);
-- Node name is ':23' = 'NEXT11'
-- Equation name is 'NEXT11', location is LC5_A12, type is buried.
NEXT11 = DFFE( _EQ004, CLK, VCC, VCC, VCC);
_EQ004 = !NEXT10 & NEXT11
# NEXT10 & !NEXT11;
-- Node name is 'SEL0'
-- Equation name is 'SEL0', type is output
SEL0 = LIE0;
-- Node name is 'SEL1'
-- Equation name is 'SEL1', type is output
SEL1 = LIE1;
-- Node name is 'SEL2'
-- Equation name is 'SEL2', type is output
SEL2 = LIE2;
-- Node name is 'SEL3'
-- Equation name is 'SEL3', type is output
SEL3 = LIE3;
-- Node name is ':1379'
-- Equation name is '_LC7_A7', type is buried
_LC7_A7 = LCELL( _EQ005);
_EQ005 = LIE0 & !LIE1 & LIE2 & LIE3;
-- Node name is ':1391'
-- Equation name is '_LC6_A10', type is buried
_LC6_A10 = LCELL( _EQ006);
_EQ006 = !LIE0 & !LIE1 & LIE2 & LIE3;
-- Node name is ':1403'
-- Equation name is '_LC4_A9', type is buried
_LC4_A9 = LCELL( _EQ007);
_EQ007 = LIE0 & LIE1 & !LIE2 & LIE3;
-- Node name is ':1415'
-- Equation name is '_LC1_A7', type is buried
_LC1_A7 = LCELL( _EQ008);
_EQ008 = !LIE0 & LIE1 & !LIE2 & LIE3;
-- Node name is ':1427'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ009);
_EQ009 = LIE0 & !LIE1 & !LIE2 & LIE3;
-- Node name is ':1439'
-- Equation name is '_LC1_A10', type is buried
_LC1_A10 = LCELL( _EQ010);
_EQ010 = !LIE0 & !LIE1 & !LIE2 & LIE3;
-- Node name is ':1451'
-- Equation name is '_LC2_A6', type is buried
!_LC2_A6 = _LC2_A6~NOT;
_LC2_A6~NOT = LCELL( _EQ011);
_EQ011 = !LIE1
# !LIE0
# !LIE2
# LIE3;
-- Node name is ':1463'
-- Equation name is '_LC1_D9', type is buried
!_LC1_D9 = _LC1_D9~NOT;
_LC1_D9~NOT = LCELL( _EQ012);
_EQ012 = !LIE1
# LIE0
# !LIE2
# LIE3;
-- Node name is ':1475'
-- Equation name is '_LC6_A1', type is buried
!_LC6_A1 = _LC6_A1~NOT;
_LC6_A1~NOT = LCELL( _EQ013);
_EQ013 = !LIE2
# LIE1
# LIE3
# !LIE0;
-- Node name is ':1487'
-- Equation name is '_LC8_A1', type is buried
!_LC8_A1 = _LC8_A1~NOT;
_LC8_A1~NOT = LCELL( _EQ014);
_EQ014 = !LIE2
# LIE1
# LIE3
# LIE0;
-- Node name is ':1499'
-- Equation name is '_LC4_A1', type is buried
!_LC4_A1 = _LC4_A1~NOT;
_LC4_A1~NOT = LCELL( _EQ015);
_EQ015 = !LIE1
# !LIE0
# LIE3
# LIE2;
-- Node name is ':1604'
-- Equation name is '_LC3_D9', type is buried
_LC3_D9 = LCELL( _EQ016);
_EQ016 = LIE0 & !LIE1 & LIE2 & LIE3
# !LIE0 & !LIE1 & !LIE2 & LIE3;
-- Node name is ':1655'
-- Equation name is '_LC8_A3', type is buried
_LC8_A3 = LCELL( _EQ017);
_EQ017 = _LC3_D9 & _LC6_A3
# _LC8_A1;
-- Node name is '~1657~1'
-- Equation name is '~1657~1', location is LC6_A3, type is buried.
-- synthesized logic cell
_LC6_A3 = LCELL( _EQ018);
_EQ018 = !_LC1_D9 & !_LC2_A6 & !_LC6_A1;
-- Node name is ':2929'
-- Equation name is '_LC6_A9', type is buried
_LC6_A9 = LCELL( _EQ019);
_EQ019 = _LC4_A9
# _LC1_A7
# _LC2_A1;
-- Node name is ':5480'
-- Equation name is '_LC3_A9', type is buried
_LC3_A9 = LCELL( _EQ020);
_EQ020 = LIE0 & !LIE1 & LIE2
# LIE1 & LIE2 & !LIE3
# !LIE2 & LIE3
# !LIE1 & LIE3;
-- Node name is ':5627'
-- Equation name is '_LC6_A12', type is buried
_LC6_A12 = LCELL( _EQ021);
_EQ021 = !NEXT10 & NEXT11;
-- Node name is ':5635'
-- Equation name is '_LC4_A12', type is buried
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