guide_tech2a.txt

nintendo64 survival document

2a. Practice - Shiren 2


This time, we talk to a villager. VWF tiles.

Address = 20000000, Offset = 0023ec80
320x8, 4-bit I. $500 bytes.

; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Three lines of dialogue at RAM location. The terms are backwards. >.<

Write RAM, addr = 2023EF18, PC=80082F90
Read RAM, addr = 8023EF18, PC=80082F9C

Write RAM, addr = 2023EE78, PC=80082FC0
Read RAM, addr = 8023EE78, PC=80082FDC

Write RAM, addr = 2023EF1C, PC=80082F84
Read RAM, addr = 8023EF1C, PC=80082F9C

Write RAM, addr = 2023EF23, PC=80082FD0
Read RAM, addr = 8023EF23, PC=80082FDC

VWF code appears below.

; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

More interestingly, the font should likely be in ROM uncompressed.

80029c44: PI Copy CART to RDRAM 136b ($88) from B016D2D6 to 80165980
80029c44: PI Copy CART to RDRAM 136b ($88) from B016B08C to 80165980
80029c44: PI Copy CART to RDRAM 136b ($88) from B0157F10 to 80165980
80029c44: PI Copy CART to RDRAM 136b ($88) from B015814A to 80165980

Looks like some header bytes - shows up as pixels.

On really close examination, we see shadow pixels in-game.
So the font uses lots of different colors.

; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

; VWF: Importantly, data is 4-bit linear storage (!)
;      So (1234)(1234) equals two pixels. This isn't planar math.

[1aa0:0013] 80083194: BLEZ    s5[0000000E],r0[00000000],800831E4h       
[0000:802d] 80083198: DADDU   s0[00000000],r0[00000000],r0[00000000]    

[0014:1400] 8008319C: SLL     v0[00000070],s4[00000030],0010h           
[0002:a403] 800831A0: SRA     s4[00000030],v0[00300000],0010h           
[0013:1400] 800831A4: SLL     v0[00300000],s3[0000000C],0010h           

; ---------------------------------------------------------------------

[0002:1403] 800831A8: SRA     v0[000C0000],v0[000C0000],0010h           
[0440:0006] 800831AC: BLTZ    v0[0000000C],800831C8h                    
[2652:fff8] 800831B0: ADDIU   s2[801659F2],s2[801659F2],FFFFFFF8h       

[0054:102a] 800831B4: SLT     v0[0000000C],v0[0000000C],s4[00000030]    
[1040:0003] 800831B8: BEQ     v0[00000001],r0[00000000],800831C8h       
[0220:202d] 800831BC: DADDU   a0[0000000C],s1[0000E128],r0[00000000]    

[0c02:0bcf] 800831C0: JAL     80082F3C                                  
[0240:282d] 800831C4: DADDU   a1[00000006],s2[801659EA],r0[00000000]    

[2631:fec0] 800831C8: ADDIU   s1[0000E128],s1[0000E128],FFFFFEC0h       
[0620:0005] 800831CC: BLTZ    s1[0000DFE8],800831E4h                    
[2673:ffff] 800831D0: ADDIU   s3[0000000C],s3[0000000C],FFFFFFFFh       

; One pixel row done

[2610:0001] 800831D4: ADDIU   s0[00000000],s0[00000000],0001h           

; Continue looping if rows not done

[0215:102a] 800831D8: SLT     v0[00000000],s0[00000001],s5[0000000E]    

[1440:fff2] 800831DC: BNE     v0[00000001],r0[00000000],800831A8h       
[0013:1400] 800831E0: SLL     v0,s3,0010h                               
    
; =====================================================================
; =====================================================================

; Clear horizontal lcv

[0000:402d] 80082F3C: DADDU   t0[0000FF01],r0[00000000],r0[00000000]    

[0004:1fc2] 80082F40: SRL     v1[0000E128],a0[0000E128],001Fh           
[3c02:8014] 80082F44: LUI     v0[00000001],FFFF8014h                    
[8c42:e8e4] 80082F48: LW      v0[80140000],FFFFE8E4h(v0[80140000])      
[0083:1821] 80082F4C: ADDU    v1[00000000],a0[0000E128],v1[00000000]    
[0002:1080] 80082F50: SLL     v0[00000000],v0[00000000],0002h           
[3c01:801b] 80082F54: LUI     at[80000000],FFFF801Bh                    
[0022:0821] 80082F58: ADDU    at[801B0000],at[801B0000],v0[00000000]    

[8c22:9050] 80082F5C: LW      v0[00000000],FFFF9050h(at[801B0000])      
[0003:1843] 80082F60: SRA     v1[0000E128],v1[0000E128],0001h           

; Src tile address (VWF cache)

[0043:3021] 80082F64: ADDU    a2[0000000E],v0[80236A80],v1[00007094]    

; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

; Load next pair of pixels <-- a1

[90a2:0000] 80082F68: LBU     v0[80236A80],0000h(a1[801659EA])          

; Retrieve pixel #1 --> v1 (upper 4)
; Retrieve pixel #2 --> a3 (lower 4) [see delay slot]

[0002:1902] 80082F6C: SRL     v1[00007094],v0[00000000],0004h           

; ---------------------------------------------------------------------

; If blank pixel #1, skip VWF code

[1060:000b] 80082F70: BEQ     v1[00000000],r0[00000000],80082FA0h       
[3047:000f] 80082F74: ANDI    a3[00000000],v0[00000000],000Fh           

; a0 is even --> store to first 4-bits of VWF 'tile' (byte)
; a0 is odd  --> store to last  4-bits of VWF 'tile' (byte)

[3082:0001] 80082F78: ANDI    v0[000000F0],a0[0000E12A],0001h           
[5040:0004] 80082F7C: BEQL    v0[00000000],r0[00000000],80082F90h       
[0003:1900] 80082F80: SLL     v1[0000000F],v1[0000000F],0004h           

; Load upper 4-bits of VWF cache

[90c2:0000] 80082F84: LBU     v0[00000001],0000h(a2[8023DB1A])          
[0802:0be6] 80082F88: J       80082F98                                  
[3042:00f0] 80082F8C: ANDI    v0[00000000],v0[00000000],00F0h           

; Load lower 4-bits of VWF cache

[90c2:0000] 80082F90: LBU     v0[00000000],0000h(a2[8023DB15])          
[3042:000f] 80082F94: ANDI    v0[00000000],v0[00000000],000Fh           

; Add old pixel and store new

[0043:1025] 80082F98: OR      v0[00000000],v0[00000000],v1[000000F0]    
[a0c2:0000] 80082F9C: SB      v0[000000F0],0000h(a2[8023DB15])          

; Bump VWF cursor position (even/odd alignment)

[2484:0001] 80082FA0: ADDIU   a0[0000E128],a0[0000E128],0001h           

; Bump VWF dst ptr

[3082:0001] 80082FA4: ANDI    v0[00000000],a0[0000E129],0001h           
[5040:0001] 80082FA8: BEQL    v0[00000001],r0[00000000],80082FB0h       
[24c6:0001] 80082FAC: ADDIU   a2[8023DB1A],a2[8023DB1A],0001h           

; --------------------------------------------------------------------

; If blank pixel #2, skip VWF code (and bump VWF cursor)

[50e0:000c] 80082FB0: BEQL    a3[00000000],r0[00000000],80082FE4h       
[2484:0001] 80082FB4: ADDIU   a0[0000E129],a0[0000E129],0001h           

; a0 is even --> store to first 4-bits of VWF 'tile' (byte)
; a0 is odd  --> store to last  4-bits of VWF 'tile' (byte)

[1040:0005] 80082FB8: BEQ     v0[00000001],r0[00000000],80082FD0h       
[0007:1900] 80082FBC: SLL     v1[000000F0],a3[0000000F],0004h           

; Load upper 4-bits of VWF cache

[90c2:0000] 80082FC0: LBU     v0[00000001],0000h(a2[8023DB18])          
[3042:00f0] 80082FC4: ANDI    v0[000000F0],v0[000000F0],00F0h           

; Add old pixel and store new

[0802:0bf7] 80082FC8: J       80082FDC                                  
[00e2:1025] 80082FCC: OR      v0[000000F0],a3[0000000F],v0[000000F0]    


; Load lower 4-bits of VWF cache

[90c2:0000] 80082FD0: LBU     v0[00000000],0000h(a2[8023DB1B])          
[3042:000f] 80082FD4: ANDI    v0[00000000],v0[00000000],000Fh           

; Add old pixel

[0043:1025] 80082FD8: OR      v0[00000000],v0[00000000],v1[00000070]    

; Store new result

[a0c2:0000] 80082FDC: SB      v0[000000FF],0000h(a2[8023DB18])          

; Bump VWF cursor position (even/odd alignment)

[2484:0001] 80082FE0: ADDIU   a0[0000E131],a0[0000E131],0001h           

; Bump VWF dst ptr

[3082:0001] 80082FE4: ANDI    v0[00000001],a0[0000E12A],0001h           
[5040:0001] 80082FE8: BEQL    v0[00000000],r0[00000000],80082FF0h       
[24c6:0001] 80082FEC: ADDIU   a2[8023DB14],a2[8023DB14],0001h           

; --------------------------------------------------------------------

; Two more pixels done --> t0 + 2

[2508:0002] 80082FF0: ADDIU   t0[00000000],t0[00000000],0002h           

; Loop through 16 pixels in row (check t0)
; Bump src ptr --> a1 + 1

[2902:0010] 80082FF4: SLTI    v0[00000000],t0[00000002],0010h           
[1440:ffdb] 80082FF8: BNE     v0[00000001],r0[00000000],80082F68h       
[24a5:0001] 80082FFC: ADDIU   a1[801659EA],a1[801659EA],0001h           

; Exit

[03e0:0008] 80083000: JR      ra[800831C8]                              
[0000:0000] 80083004: NOP