📄 hcc2.mdl
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SourceType "Discrete PI Controller"
ShowPortLabels on
Kp "4"
Ki ".02"
Par_Limits "[1e6 -1e6]"
Init "0"
Ts "50e-6"
}
Block {
BlockType Reference
Name "Discrete\nPI Controller1"
Ports [1, 1]
Position [490, 322, 535, 368]
SourceBlock "powerlib_extras/Discrete \nControl Blocks/D"
"iscrete\nPI Controller"
SourceType "Discrete PI Controller"
ShowPortLabels on
Kp "4"
Ki ".02"
Par_Limits "[1e6 -1e6]"
Init "0"
Ts "50e-6"
}
Block {
BlockType Reference
Name "Discrete\nVirtual PLL"
Ports [0, 3]
Position [25, 273, 90, 337]
SourceBlock "powerlib_extras/Discrete \nControl Blocks/D"
"iscrete\nVirtual PLL"
SourceType "Discrete Virtual PLL"
ShowPortLabels on
Freq "60"
Phase "0"
Ts "50e-6"
}
Block {
BlockType Reference
Name "Discrete\nVirtual PLL1"
Ports [0, 3]
Position [305, 503, 370, 567]
SourceBlock "powerlib_extras/Discrete \nControl Blocks/D"
"iscrete\nVirtual PLL"
SourceType "Discrete Virtual PLL"
ShowPortLabels on
Freq "60"
Phase "0"
Ts "50e-6"
}
Block {
BlockType Reference
Name "Discrete SV PWM\nGenerator"
Ports [2, 1]
Position [875, 235, 940, 295]
SourceBlock "powerlib_extras/Discrete \nControl Blocks/D"
"iscrete SV PWM\nGenerator"
SourceType "Discrete SV PWM Generator"
ShowPortLabels on
InputType "alpha-beta components"
SwitchingPattern "Pattern #1"
Fc "2000"
ParUref "[0.8 -30 50]"
Ts "2e-6"
}
Block {
BlockType From
Name "From1"
Position [295, 465, 340, 485]
BackgroundColor "[0.501961, 1.000000, 1.000000]"
ShowName off
DialogController "Simulink.DDGSource"
CloseFcn "tagdialog Close"
GotoTag "Vabc"
}
Block {
BlockType From
Name "From2"
Position [15, 235, 60, 255]
BackgroundColor "[0.501961, 1.000000, 1.000000]"
ShowName off
DialogController "Simulink.DDGSource"
CloseFcn "tagdialog Close"
GotoTag "Iabc"
}
Block {
BlockType Step
Name "Id"
Position [330, 238, 360, 262]
ForegroundColor "blue"
Time ".025"
Before "10"
After "20"
SampleTime "0"
}
Block {
BlockType Step
Name "Iq"
Position [330, 333, 360, 357]
ForegroundColor "blue"
Time ".025"
Before "10"
After "20"
SampleTime "0"
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [410, 240, 430, 260]
ShowName off
IconShape "round"
Inputs "|+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [410, 335, 430, 355]
ShowName off
IconShape "round"
Inputs "|+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Sum2"
Ports [2, 1]
Position [550, 240, 570, 260]
ShowName off
IconShape "round"
Inputs "|+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Sum3"
Ports [2, 1]
Position [590, 325, 610, 345]
ShowName off
IconShape "round"
Inputs "|+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Terminator
Name "Terminator"
Position [280, 312, 300, 328]
ShowName off
}
Block {
BlockType Terminator
Name "Terminator1"
Position [560, 542, 580, 558]
ShowName off
}
Block {
BlockType Reference
Name "abc_to_dq0\nTransformation"
Ports [2, 1]
Position [135, 255, 200, 355]
SourceBlock "powerlib_extras/Measurements/abc_to_dq0\nTr"
"ansformation"
SourceType "abc to dq0 Transformation"
ShowPortLabels on
Port {
PortNumber 1
Name "Vd Vq V0"
PropagatedSignals "Vd, Vq, "
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Reference
Name "abc_to_dq0\nTransformation1"
Ports [2, 1]
Position [415, 485, 480, 585]
SourceBlock "powerlib_extras/Measurements/abc_to_dq0\nTr"
"ansformation"
SourceType "abc to dq0 Transformation"
ShowPortLabels on
Port {
PortNumber 1
Name "Vd Vq V0"
PropagatedSignals "Vd, Vq, "
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
ShowSigGenPortName on
}
}
Block {
BlockType Outport
Name "pulses"
Position [1030, 258, 1060, 272]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "Discrete\nPI Controller"
DstPort 1
}
Line {
SrcBlock "Id"
SrcPort 1
DstBlock "Sum"
DstPort 1
}
Line {
Name "Vd Vq V0"
SrcBlock "abc_to_dq0\nTransformation"
SrcPort 1
DstBlock "Demux"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 3
DstBlock "Terminator"
DstPort 1
}
Line {
SrcBlock "Discrete\nVirtual PLL"
SrcPort 2
Points [10, 0; 0, 25]
DstBlock "abc_to_dq0\nTransformation"
DstPort 2
}
Line {
SrcBlock "From2"
SrcPort 1
Points [55, 0]
DstBlock "abc_to_dq0\nTransformation"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 1
Points [160, 0]
DstBlock "Sum"
DstPort 2
}
Line {
SrcBlock "Iq"
SrcPort 1
DstBlock "Sum1"
DstPort 1
}
Line {
SrcBlock "Sum1"
SrcPort 1
DstBlock "Discrete\nPI Controller1"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 2
Points [50, 0; 0, 75; 110, 0]
DstBlock "Sum1"
DstPort 2
}
Line {
Name "Vd Vq V0"
SrcBlock "abc_to_dq0\nTransformation1"
SrcPort 1
DstBlock "Demux1"
DstPort 1
}
Line {
SrcBlock "Demux1"
SrcPort 3
DstBlock "Terminator1"
DstPort 1
}
Line {
SrcBlock "Discrete\nVirtual PLL1"
SrcPort 2
Points [10, 0; 0, 25]
DstBlock "abc_to_dq0\nTransformation1"
DstPort 2
}
Line {
SrcBlock "From1"
SrcPort 1
Points [55, 0]
DstBlock "abc_to_dq0\nTransformation1"
DstPort 1
}
Line {
SrcBlock "Discrete\nPI Controller"
SrcPort 1
DstBlock "Sum2"
DstPort 1
}
Line {
SrcBlock "Discrete\nPI Controller1"
SrcPort 1
Points [35, 0]
DstBlock "Sum3"
DstPort 1
}
Line {
SrcBlock "Demux1"
SrcPort 1
Points [20, 0]
DstBlock "Sum2"
DstPort 2
}
Line {
SrcBlock "Demux1"
SrcPort 2
Points [60, 0]
DstBlock "Sum3"
DstPort 2
}
Line {
SrcBlock "Sum2"
SrcPort 1
Points [35, 0; 0, -15; 55, 0; 0, -30; 95, 0; 0, 45]
DstBlock "Discrete SV PWM\nGenerator"
DstPort 1
}
Line {
SrcBlock "Sum3"
SrcPort 1
Points "[15, 0; 0, -80; 30, 0; 0, 30; 100, 0; 0, -1"
"5; 25, 0; 0, 10]"
DstBlock "Discrete SV PWM\nGenerator"
DstPort 2
}
Line {
SrcBlock "Discrete SV PWM\nGenerator"
SrcPort 1
DstBlock "pulses"
DstPort 1
}
}
}
Block {
BlockType Reference
Name "I A"
Ports [0, 1, 0, 0, 0, 1, 1]
Position [425, 248, 450, 272]
Orientation "left"
NamePlacement "alternate"
SourceBlock "powerlib/Measurements/Current Measurement"
SourceType "Current Measurement"
ShowPortLabels on
PhasorSimulation off
OutputType "Complex"
PSBequivalent "0"
}
Block {
BlockType Reference
Name "I B"
Ports [0, 1, 0, 0, 0, 1, 1]
Position [380, 293, 405, 317]
Orientation "left"
NamePlacement "alternate"
SourceBlock "powerlib/Measurements/Current Measurement"
SourceType "Current Measurement"
ShowPortLabels on
PhasorSimulation off
OutputType "Complex"
PSBequivalent "0"
}
Block {
BlockType Reference
Name "I C"
Ports [0, 1, 0, 0, 0, 1, 1]
Position [350, 348, 375, 372]
Orientation "left"
NamePlacement "alternate"
SourceBlock "powerlib/Measurements/Current Measurement"
SourceType "Current Measurement"
ShowPortLabels on
PhasorSimulation off
OutputType "Complex"
PSBequivalent "0"
}
Block {
BlockType Reference
Name "IGBT Inverter"
Ports [1, 0, 0, 0, 0, 3, 2]
Position [735, 226, 800, 319]
BackgroundColor "orange"
AttributesFormatString "\\n"
SourceBlock "powerlib/Power\nElectronics/Universal Bridge"
SourceType "Universal Bridge"
ShowPortLabels on
Arms "3"
SnubberResistance "1000"
SnubberCapacitance "inf"
Device "IGBT / Diodes"
Ron "1e-3"
Lon "0"
ForwardVoltages "[ 0.8 0.8 ]"
ForwardVoltage ".8"
GTOparameters "[ 1e-6 , 1e-6 ]"
IGBTparameters "[ 1e-6 , 2e-6 ]"
Measurements "None"
}
Block {
BlockType SubSystem
Name "LC Filter"
Ports [0, 0, 0, 0, 0, 3, 3]
Position [575, 247, 635, 323]
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "LC Filter"
Location [355, 141, 729, 373]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Reference
Name "2 mH "
Ports [0, 0, 0, 0, 0, 3, 3]
Position [100, 50, 155, 100]
AttributesFormatString "\\n"
SourceBlock "powerlib/Elements/Three-Phase\nSeries RLC B"
"ranch"
SourceType "Three-Phase Series RLC Branch"
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