pll_init.c

本人s12的一部分机器人巡线程序

/*********************************************************************/
/*********************************************************************/

/* PLL_Init.c   ------------ Hardware related functions                   

		PLL_Init();

**********************************************************************/
/******************PLL_Init()****************/
void PLL_Init(uchar synr,uchar refdv)// PLLOSC = xx MHz
  {
    SYNR=synr;
    REFDV=refdv; //PLLCLK = 2 * OSCCLK * (SYNR + 1) / (REFDV + 1)
 	  CLKSEL=0x00;
    PLLCTL=0xD1;
    while((CRGFLG&0x08)==0);// Wait for PLLCLK to stabilize.
    CLKSEL=0x80;// Switch to PLL cloc
  /*Meaning for CLKSEL:
  Bit 7: PLLSEL = 0 Keep using OSCCLK until we are ready to switch to PLLCLK
  Bit 6: PSTP   = 0 Do not need to go to Pseudo-Stop Mode
  Bit 5: SYSWAI = 0 In wait mode system clocks stop.
  But 4: ROAWAI = 0 Do not reduce oscillator amplitude in wait mode.
  Bit 3: PLLWAI = 0 Do not turn off PLL in wait mode
  Bit 2: CWAI	= 0 Do not stop the core during wait mode
  Bit 1: RTIWAI = 0 Do not stop the RTI in wait mode
  Bit 0: COPWAI = 0 Do not stop the COP in wait mode
  */
/*Meaning for PLLCTL:
  Bit 7: CME   = 1; Clock monitor enable - reset if bad clock when set
  Bit 6: PLLON = 1; PLL On bit
  Bit 5: AUTO  = 0; No automatic control of bandwidth, manual through ACQ
  But 4: ACQ   = 1; 1 for high bandwidth filter (acquisition); 0 for low (tracking)
  Bit 3:            (Not Used by 9s12c32)
  Bit 2: PRE   = 0; RTI stops during Pseudo Stop Mode
  Bit 1: PCE   = 0; COP diabled during Pseudo STOP mode
  Bit 0: SCME  = 1; Crystal Clock Failure -> Self Clock mode NOT reset.
  
  */
//   no PLL (crystal) -> SYSCLOCK = 4 MHz   -> BUSCLOCK = 2 MHz
//   PLL on           -> SYSCLOCK = 48 MHz  -> BUSCLOCK = 24 MHz
  }