hardware.c

嵌入式TCP/IP模块

#define HARDWARE_GLOBALS
#include "../boot/config.h"
#include "../include/cfg_net.h"

/**************************************************************/
void udelay(uint8 T)
{
 uint16 i;
 for(;T>0;T--)
    for(i=0;i<5750;i++);
}
/*********************************************************/
/*********************************************************/
void outb_cmd(u8 reg)
{
   uint32 a;   
   a=reg;
   a<<=16;
   IO0SET=INACTION;              //禁止读写
   IO0CLR=CLRPORT;              //数据线清零 
   IO0DIR=DATAOUT;             //数据地址线为输出
   IO0SET=a; 
   IO0CLR=CMD;                   //输出低
   IO0CLR=CS;                   //输出低      
   IO0CLR=WR;                   //输出低
   __asm{
      nop
      nop
      nop
      nop
      nop
   }
   IO0SET=WR;                   //输出高
   IO0SET=CS;
   IO0SET=CMD;
   //IO0DIR&=DATAIN;              //数据线输入 
}
/**********************************************************
***********************************************************/
void outb_data(u8 data)
{
   uint32 a;   
   a=data;
   a<<=16;
   IO0SET=INACTION;              //禁止读写
   IO0CLR=CLRPORT;              //数据线清零 
   IO0DIR|=DATAOUT;             //数据地址线为输出
   IO0SET=a; 
   IO0CLR=CS;                   //输出低      
   IO0CLR=WR;                   //输出低
   __asm{
      nop
      nop
      nop
      nop
      nop
   }
   IO0SET=WR;                   //输出高
   IO0SET=CS;
  // IO0DIR&=DATAIN;              //数据线输入 
}

/**********************************************************
***********************************************************/
u8 inb_data(void)
{
   uint8 i; 
   uint32 a;
   IO0SET=INACTION;              //禁止读写
   IO0CLR=CLRPORT;              //数据地址线清零 
   IO0DIR=DATAIN;              //数据线输入     
   IO0CLR=CS;                   //输出低     
   IO0CLR=RD;                   //输出低
   __asm{
      nop
      nop
      nop
      nop
      nop
   }
   a=IO0PIN;
   a&=0x00ff0000;        //读端口数据   
   IO0SET=RD;                  //输出高
   IO0SET=CS;   
   IO0DIR|=DATAOUT;             //数据地址线为输出   
   a>>=16;
   i=a;   
   return (i);
}




/*
   Read a byte from I/O port
*/
static u8 DM9000_ior(int reg)
{
	outb_cmd(reg);
	return inb_data();
}

/*
   Write a byte to I/O port
*/
static void DM9000_iow(int reg, u8 value)
{
	outb_cmd(reg);
	outb_data(value);
}     

/* General Purpose dm9000 reset routine *********************************************/
static void dm9000_reset(void)
{
	DM9000_iow(DM9000_NCR, 0x03);
	udelay(1);		/* delay 1ms */
}
/*Search DM9000 board, allocate space and register it***********************************/
int dm9000_probe(void)
{
	u32 id_val;
	id_val = DM9000_ior(DM9000_VIDL);
	id_val |= DM9000_ior(DM9000_VIDH) << 8;
	id_val |= DM9000_ior(DM9000_PIDL) << 16;
	id_val |= DM9000_ior(DM9000_PIDH) << 24;
	if (id_val == DM9000_ID) 
		return 1;
	else 
		return 0;
}
/*
   Write a word to phyxcer
*/
static void phy_write(int reg, u16 value)
{
	/* Fill the phyxcer register into REG_0C */
	DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);

	/* Fill the written data into REG_0D & REG_0E */
	DM9000_iow(DM9000_EPDRL, (value & 0xff));
	DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
	DM9000_iow(DM9000_EPCR, 0xa);	/* Issue phyxcer write command */
	udelay(250);		/* Wait write complete */
	DM9000_iow(DM9000_EPCR, 0x0);	/* Clear phyxcer write command */
}
/* Set PHY operationg mode */

static void set_PHY_mode(void)
{
    u8 media_mode;
	u16 phy_reg4 = 0x01e1;
	u16 phy_reg0 = 0x1000;
	
	phy_write(0, 0x8000);
	udelay(3);
	
	media_mode=DM9000_10MFD;
	if (!(media_mode & DM9000_AUTO)) 
	{
		switch (media_mode)
		{
		case DM9000_10MHD:
			phy_reg4 = 0x21;
			phy_reg0 = 0x0000;
			break;
		case DM9000_10MFD:
			phy_reg4 = 0x41;
			phy_reg0 = 0x1100;
			break;
		case DM9000_100MHD:
			phy_reg4 = 0x81;
			phy_reg0 = 0x2000;
			break;
		case DM9000_100MFD:
			phy_reg4 = 0x101;
			phy_reg0 = 0x3100;
			break;
		}
		phy_write(4, phy_reg4);	/* Set PHY media mode */
		phy_write(0, phy_reg0);	/*  Tmp */		
	}
} 

/****************************************************************
**函数原型：    unsigned char * Rec_Packet()
**入口参数: