📄 rc632reg.h
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/****************************************************************************
*
* File: RC500REG.H(HEADER for RC500 Register and Commaands)
*
* Created: 2002.12.25
*
* Editor JOHN CHENG
*
* Compiler: KEIL C51 V7.00
*
* Description: T89C51RD2-Firmware for RC500 Serial Reader
*
*****************************************************************************
*
* Version | Date | PCB | Description
* --------+----------+-------+------------------------------------------------
* V100 | 25/12/02 | | Initial version,TypeA and TypeB
* V110 | 15/01/03 | | reset pin control by FIFO out pins.Adding two new command
* | | | (READ EEPROM C6 and WRITE EEPROM C7).
* | | | delay using a fixed time,not "for loop".
* | | | New routine funtions is generated in main funtion.
* V120 | 20/01/03 | | Modify reader.h,adding rc500cmd.h
* V130 | 08/02/03 | | Adding some funtions about SAM
* | | |
****************************************************************************/
//Register of MFRC500
#define ChipRC632 0x7F00
// PAGE 0 Command and Status
#define RegPage XBYTE[ChipRC632 + 0x00]
#define RegCommand XBYTE[ChipRC632 + 0x01]
#define RegFIFOData XBYTE[ChipRC632 + 0x02]
#define RegPrimaryStatus XBYTE[ChipRC632 + 0x03]
#define RegFIFOLength XBYTE[ChipRC632 + 0x04]
#define RegSecondaryStatus XBYTE[ChipRC632 + 0x05]
#define RegInterruptEn XBYTE[ChipRC632 + 0x06]
#define RegInterruptRq XBYTE[ChipRC632 + 0x07]
// PAGE 1 Control and Status
#define RegPage1 XBYTE[ChipRC632 + 0x08]
#define RegControl XBYTE[ChipRC632 + 0x09]
#define RegErrorFlag XBYTE[ChipRC632 + 0x0a]
#define RegCollPos XBYTE[ChipRC632 + 0x0b]
#define RegTimerValue XBYTE[ChipRC632 + 0x0c]
#define RegCRCResultLSB XBYTE[ChipRC632 + 0x0d]
#define RegCRCResultMSB XBYTE[ChipRC632 + 0x0e]
#define RegBitFraming XBYTE[ChipRC632 + 0x0f] //Different from the rc500 and the value shall not be changed
// PAGE 2 Transmitter and Coder Control
#define RegPage2 XBYTE[ChipRC632 + 0x10]
#define RegTxControl XBYTE[ChipRC632 + 0x11]
#define RegCwConductance XBYTE[ChipRC632 + 0x12]
#define RegModConductance XBYTE[ChipRC632 + 0x13] //Different from the rc500
#define RegCoderControl XBYTE[ChipRC632 + 0x14]
#define RegModWidth XBYTE[ChipRC632 + 0x15]
#define RegModWidthSOF XBYTE[ChipRC632 + 0x16] //Different from the rc500
#define TypeBFraming XBYTE[ChipRC632 + 0x17] //the value shall not be changed
// PAGE 3 Receiver and Decoder Control
#define RegPage3 XBYTE[ChipRC632 + 0x18]
#define RegRxControl1 XBYTE[ChipRC632 + 0x19]
#define RegDecoderControl XBYTE[ChipRC632 + 0x1a]
#define RegBitPhase XBYTE[ChipRC632 + 0x1b]
#define RegRxThreshold XBYTE[ChipRC632 + 0x1c]
#define RFU1D XBYTE[ChipRC632 + 0x1d]
#define RegRxControl2 XBYTE[ChipRC632 + 0x1e]
#define RegClockQControl XBYTE[ChipRC632 + 0x1f]
// PAGE 4 RF-Timing and Channel Redundancy
#define RegPage4 XBYTE[ChipRC632 + 0x20]
#define RegRxWait XBYTE[ChipRC632 + 0x21]
#define RegChannelRedundancy XBYTE[ChipRC632 + 0x22]
#define RegCRCPresetLSB XBYTE[ChipRC632 + 0x23]
#define RegCRCPresetMSB XBYTE[ChipRC632 + 0x24]
#define RegTimeSlotPeriod XBYTE[ChipRC632 + 0x25] //Different from the rc500
#define RegMfOutSelect XBYTE[ChipRC632 + 0x26]
#define RFU27 XBYTE[ChipRC632 + 0x27]
// PAGE 5 FIFO, Timer and IRQ-Pin Configuration
#define RegPage5 XBYTE[ChipRC632 + 0x28]
#define RegFIFOLevel XBYTE[ChipRC632 + 0x29]
#define RegTimerClock XBYTE[ChipRC632 + 0x2a]
#define RegTimerControl XBYTE[ChipRC632 + 0x2b]
#define RegTimerReload XBYTE[ChipRC632 + 0x2c]
#define RegIRqPinConfig XBYTE[ChipRC632 + 0x2d]
#define RFU2E XBYTE[ChipRC632 + 0x2e]
#define RFU2F XBYTE[ChipRC632 + 0x2f]
// PAGE 6 RFU
#define RegPage6 XBYTE[ChipRC632 + 0x30]
#define RFU31 XBYTE[ChipRC632 + 0x31]
#define RFU32 XBYTE[ChipRC632 + 0x32]
#define RFU33 XBYTE[ChipRC632 + 0x33]
#define RFU34 XBYTE[ChipRC632 + 0x34]
#define RFU35 XBYTE[ChipRC632 + 0x35]
#define RFU36 XBYTE[ChipRC632 + 0x36]
#define RFU37 XBYTE[ChipRC632 + 0x37]
// PAGE 7 Test Control
#define RegPage7 XBYTE[ChipRC632 + 0x38]
#define RFU39 XBYTE[ChipRC632 + 0x39]
#define RegTestAnaSelect XBYTE[ChipRC632 + 0x3a]
#define RFU3B XBYTE[ChipRC632 + 0x3b]
#define RFU3C XBYTE[ChipRC632 + 0x3c]
#define RegTestDigiSelect XBYTE[ChipRC632 + 0x3d]
#define RFU3E XBYTE[ChipRC632 + 0x3e]
#define RFU3F XBYTE[ChipRC632 + 0x3f]
//------------------------------------------------
//------------------------------------------------
// P C D - C O M M A N D S
#define PCD_IDLE 0x00 /*!< No action: cancel current command
or home state */
#define PCD_WRITEE2 0x01 //!< Get data from FIFO and write it to the E2PROM
#define PCD_READE2 0x03 /*!< Read data from E2PROM and put it into the
FIFO */
#define PCD_LOADCONFIG 0x07 /*!< Read data from E2PROM and initialise the
registers */
#define PCD_LOADKEYE2 0x0B /*!< Read a master key from the E2PROM and put
it into the master key buffer */
#define PCD_AUTHENT1 0x0C /*!< Perform the first part of the card
authentication using the Crypto1 algorithm.
Remark: The master key is automatically taken
from the master key buffer. this implies,
that the command LoadKeyE2 has to be executed
before using a certain key for card
authentication */
#define PCD_CALCCRC 0x12 /*!< Activate the CRC-Coprocessor
Remark: The result of the CRC calculation can
be read from the register CRCResultXXX */
#define PCD_AUTHENT2 0x14 /*!< Perform the second part of the card
authentication using the Crypto1 algorithm. */
#define PCD_RECEIVE 0x16 /*!< Activate Receiver Circuitry. Before the
receiver actually starts, the state machine
waits until the time configured in the
register RxWait has passed.
Remark: It is possible to read any received
data from the FIFO while the Receive command
is active. Thus it is possible to receive an
unlimited number of bytes by reading them
from the FIFO in timer. */
#define PCD_LOADKEY 0x19 /*!< Read a master key from the FIFO and put it
into the master key buffer
Remark: The master key has to be prepared in
a certain format. Thus, 12 byte have to be
passed to load a 6 byte master key */
#define PCD_TRANSMIT 0x1A /*!< Transmit data from FIFO to the card
Remark: If data is already in the FIFO when
the command is activated, this data is
transmitted immediately. It is possible to
write data to the FIFO while the Transmit
command is active. Thus it is possible to
transmit an unlimited number of bytes in one
stream by writting them to the FIFO in time.*/
#define PCD_TRANSCEIVE 0x1E /*!< Transmits data from FIFO to the card and
after that automatically activates the
receiver. Before the receiver actually
starts,the state machine waits until the
time configured in the register RxWait has
passed.
Remark: This command is the combination of
Transmit and Receive.*/
#define PCD_RESETPHASE 0x3F /*!< Runs the Reset- and Initialisation Phase
Remark: This command can not be activated by
software, but only by a Power-On or
Hard Reset */
//-------------------------------
// General Include File for serveral defines concerning conditional library
// compilation and microcontroller usage
#define PICC_REQIDL 0x26 //!< request idle
#define PICC_REQALL 0x52 //!< request all
#define PICC_ANTICOLL1 0x93 //!< anticollision level 1 106 kBaud
#define PICC_ANTICOLL2 0x95 //!< anticollision level 2
#define PICC_ANTICOLL3 0x97 //!< anticollision level 3
#define PICC_AUTHENT1A 0x60 //!< authentication using key A
#define PICC_AUTHENT1B 0x61 //!< authentication using key B
#define PICC_READ 0x30 //!< read block
#define PICC_WRITE 0xA0 //!< write block
#define PICC_DECREMENT 0xC0 //!< decrement value
#define PICC_INCREMENT 0xC1 //!< increment value
#define PICC_RESTORE 0xC2 //!< restore command code
#define PICC_TRANSFER 0xB0 //!< transfer command code
#define PICC_HALT 0x50 //!< halt
//---------------------------------------------------------------------------------------------------
// default value for Type B frame
// Type B commands
#define TypeB_Request 0x05
#define TypeB_Attrib 0x1d
#define TypeB_Halt 0x50
// Default Parameter values for ATTRIB command
#define TypeB_Param1 0x00
#define TypeB_Param2 0x02
#define TypeB_Param3 0x01
//default Parameter values for 15693 command
#define ISO15693_INVENTORY 0x01
#define ISO15693_STAY_QUIET 0x02
#define ISO15693_READ_SINGLE_BLOCK 0x20
#define ISO15693_WRITE_SINGLE_BLOCK 0x21
#define ISO15693_LOCK_BLOCK 0x22
#define ISO15693_READ_MULTIPLE_BLOCKS 0x23
#define ISO15693_WRITE_MULTIPLE_BLOCKS 0x24
#define ISO15693_SELECT 0x25
#define ISO15693_RESET_TO_READY 0x26
#define ISO15693_WRITE_AFI 0x27
#define ISO15693_LOCK_AFI 0x28
#define ISO15693_WRITE_DSFID 0x29
#define ISO15693_LOCK_DSFID 0x2A
#define ISO15693_GET_SYSTEM_INFO 0x2B
#define ISO15693_GET_MULTIPLE_BLOCK_SECURITY 0x2C
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