slf9000.h

很强的射频卡reader源代码

/****************************************************************************
*                                                                           
* File:         SLF9000.H(HEADER for SLF900 REGISTER AND Function Prototype)                                     
*                                                                           
* Created:      2003.1.20                                                    
*                                                                           
* Editor        JOHN CHENG
*                                                                           
* Compiler:     KEIL C51 V7.00                                              
*                                                                           
* Description:  T89C51RD2-Firmware for Infineon Serial Reader               
*                                                                           
*****************************************************************************
*                                                                           
* Version | Date     |  PCB  | Description                                          
* --------+----------+-------+------------------------------------------------ 
* V100    | 25/12/02 | 00.01 | Initial version,TypeA and TypeB 
* V110    | 15/01/03 | 00.02 | reset pin control by FIFO out pins.Adding two new command
*         |          |       | (READ EEPROM C6 and WRITE EEPROM C7).
*         |          |       | delay using a fixed time,not "for loop".
*         |          |       | New routine funtions is generated in main funtion.          
* V120    | 20/01/03 |       | Modify reader.h,adding rc500cmd.h	    
* V130    | 08/02/03 |       | Adding some funtions about SAM
*         |          |       |                                            
****************************************************************************/

//Below define Infineon IC chip SLF9000
#define 	slfData		XBYTE[0xBF00] 
 

typedef struct
{
  byte DAT;          //128 bytes FIFO
  byte MOD;          //ECD ACR CCR APY CPY DIV SYT SYR
  byte CMD;          //CLF CLT STT --- IVI ERF STR ERC     
  byte Status;       //FIE FIF --- --- DER FEF PYE CRE
  byte IntMask;      //TC  RC  CD  FD  TO  SR
  byte IntStatus;    //TC  RC  CD  FD  TO  SR
  byte BCNTR_LSB;    //lower byte of bit count receive 
  byte BCNTS_LSB;    //lower byte of bit count transmit.
  byte CRC_MSB;      //upper byte of CRC check byte
  byte CRC_LSB;      //lower byte of CRC check byte.
  byte GAP;          //number of clocks.
  byte VPL;          //valid pulse length
  byte SPO;          //--- --- CD  ULD RC  TRF COUNT CDIV   Supress output.
  byte Null_D;       //space address
  byte CSU;          //CRC start upper value.
  byte CSL;          //CRC start lower value.
  byte Null_0x10;    //space address.
  byte EMD;          //SOR SM  DM  SCR CODE............  Extended modes
  byte EGT;          //--- --- --- --- Guard time for downlink.
  byte Null_0x13;
  byte TIU;          //Timer upper byte.
  byte TIL;          //Timer lower byte.
  byte BCNTR_MSB;    //Upper byte of bit count receive.
  byte BCNTS_MSB;    //Upper byte of bit count transmit.
  byte SOF;          //Start of frame
  byte LIN;          //lead in synctronization point.
  byte IBF;          //Invalid bit form.
  byte EPS;          //End of frame/pulse width.
  byte Null_0x1C;
  byte Null_0x1D;
  byte ETY;          //Encoder type.
  byte DTY;          //Decoder type.
}SLF900;


//Below is reigister "MOD"
#define ECD	0x80
#define ACR 0x40
#define CCR 0x20
#define APY 0x10
#define CPY 0x08
#define DIV 0x04
#define SYT 0x02
#define SYR 0x01

//Below is Command register
#define CLF 0x80
#define CLT 0x40
#define STT 0x20
#define IVI 0x08
#define ERF 0x04  //Enable RF
#define STR 0x02  //Enable transmit 
#define ERC 0x01  //Enable receive data 

//Below is Status register
#define FIE 0x80
#define FIF 0x40
#define DER 0x08
#define FEF 0x04
#define PYE 0x02
#define CRE 0x01

//Below is 'Interrupt Status' register (IRS)
#define TC  0x80
#define RC  0x40
#define CD  0x20
#define FD  0x10
#define TO  0x08
#define SR  0x04

//Below is 'Suppress output signal (SPO)
#define SPO_CD   0x20
#define SPO_ULD  0x10
#define SPO_RC   0x08
#define SPO_TRF  0x04
#define SPO_COUT 0x02
#define SPO_CDIV 0x01

//Below is 'Extended modes' register (EMD)
#define EMD_SOR 0x80
#define EMD_SM  0x40
#define EMD_DM  0x20
#define EMD_SCR 0x10
#define EMD_3   0x08
#define EMD_2   0x04
#define EMD_1   0x02
#define EMD_0   0x01

//Below function define Infineon chip IC  
extern void 		 Initial_SLF900(void);
extern void 		 inf_Timer(unsigned char value);  
extern unsigned char inf_Request(unsigned char mode,unsigned char *buffer);
extern unsigned char inf_Anticoll(unsigned char *buffer);
extern unsigned char inf_Select(unsigned char *buffer);
extern unsigned char inf_Halt(unsigned char mode);
extern void 		 inf_WaitCardReply(unsigned char time);

extern unsigned char inf_Read(unsigned char pAddress,unsigned char nByte,unsigned char *Buffer);
extern unsigned char Inf_Write(unsigned char pAddress);
extern unsigned char inf_RestrictWrite(unsigned char pAddress,unsigned char mode,unsigned char *Buffer);
extern unsigned char inf_WriteRead(unsigned char pAddress,unsigned char mode,unsigned char *Buffer);
extern unsigned char inf_ResWriteRead(unsigned char pAddress,unsigned char mode,unsigned char *Buffer);
extern void 		 Reply_NACK(void);